Guy G. Lemieux

32 papers A* 2A 16B 5Journal 5Unranked 4

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	MPTorch-FPGA: A Custom Mixed-Precision Framework for FPGA-Based DNN Training. DATE Sami Ben Ali, Silviu-Ioan Filip, Olivier Sentieys, Guy G. Lemieux
2011	A	`conf`	A CAD framework for Malibu: an FPGA with time-multiplexed coarse-grained elements. FPGA David Grant, Chris C. Wang, Guy G. Lemieux
2011	J	`jnl`	Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs (MPSAs). IEEE Trans. Very Large Scale Integr. Syst. Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton
2011	A	`conf`	Scalable and deterministic timing-driven parallel placement for FPGAs. FPGA Chris C. Wang, Guy G. Lemieux
2011	A	`conf`	The role of FPGAs in a converged future with heterogeneous programmable processors: pre-conference workshop. FPGA Jonathan Rose, Guy G. Lemieux
2011	A	`conf`	VEGAS: soft vector processor with scratchpad memory. FPGA Christopher Han-Yu Chou, Aaron Severance, Alex D. Brant, Zhiduo Liu, Saurabh Sant, Guy G. Lemieux
2010	A	`conf`	The impact of interconnect architecture on via-programmed structured ASICs (VPSAs). FPGA Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton
2009	—	`conf`	Estimating reliability and throughput of source-synchronous wave-pipelined interconnect. NOCS Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet
2009	A	`conf`	PERG-Rx: a hardware pattern-matching engine supporting limited regular expressions. FPGA Johnny Tsung Lin Ho, Guy G. Lemieux
2009	B	`conf`	Replace: An incremental placement algorithm for field programmable gate arrays. FPL David Leong, Guy G. Lemieux
2009	A	`conf`	Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs. FPGA Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet
2009	J	`jnl`	Vector Processing as a Soft Processor Accelerator. ACM Trans. Reconfigurable Technol. Syst. Jason Yu, Christopher Eagleston, Christopher Han-Yu Chou, Maxime Perreault, Guy G. Lemieux
2008	A	`conf`	Designing with extreme parallelism. FPGA Guy G. Lemieux, Tarek A. El-Ghazawi
2008	A	`conf`	Extreme parallel architectures for the masses. FPGA Tarek A. El-Ghazawi, Guy G. Lemieux
2008	J	`jnl`	GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering. IEEE Trans. Very Large Scale Integr. Syst. Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton
2008	J	`jnl`	Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing. ACM Trans. Reconfigurable Technol. Syst. David Grant, Guy G. Lemieux
2008	A	`conf`	Vector processing as a soft-core CPU accelerator. FPGA Jason Yu, Guy G. Lemieux, Christopher Eagleston
2007	J	`jnl`	A Survey and Taxonomy of GALS Design Styles. IEEE Des. Test Comput. Paul Teehan, Mark R. Greenstreet, Guy G. Lemieux
2007	—	`conf`	Congestion estimation and localization in FPGAS: a visual tool for interconnect prediction. SLIP David Yeager, Darius Chiu, Guy G. Lemieux
2007	A	`conf`	GlitchLess: an active glitch minimization technique for FPGAs. FPGA Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton
2006	B	`conf`	Semi-Synthetic Circuit Generation Using Graph Monomorphism for Testing Incremental Placement and Incremental Routing Tools. FPL David Grant, Scott Chin, Guy G. Lemieux
2006	A	`conf`	Un/DoPack: re-clustering of large system-on-chip designs with interconnect variation for low-cost FPGAs. ICCAD Marvin Tom, David Leong, Guy G. Lemieux
2005	B	`conf`	Defect-Tolerant FPGA Switch Block and Connection Block with Fine-Grain Redundancy for Yield Enhancement. FPL Anthony J. Yu, Guy G. Lemieux
2005	—	`conf`	FPGA Defect Tolerance: Impact of Granularity. FPT Anthony J. Yu, Guy G. Lemieux
2005	A*	`conf`	Logic block clustering of large designs for channel-width constrained FPGAs. DAC Marvin Tom, Guy G. Lemieux
2002	B	`conf`	Analytical Framework for Switch Block Design. FPL Guy G. Lemieux, David M. Lewis
2002	A	`conf`	Circuit design of routing switches. FPGA Guy G. Lemieux, David M. Lewis
2001	A	`conf`	Using sparse crossbars within LUT. FPGA Guy G. Lemieux, David M. Lewis
2000	A	`conf`	Generating highly-routable sparse crossbars for PLDs. FPGA Guy G. Lemieux, Paul Leventis, David M. Lewis
2000	B	`conf`	The NUMAchine Multiprocessor. ICPP R. Grindley, Tarek S. Abdelrahman, Stephen Brown, S. Caranci, D. DeVries, Benjamin Gamsa, A. Grbic, M. Gusat, R. Ho, Orran Krieger, Guy G. Lemieux, K. Loveless, Naraig Manjikian, P. McHardy, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic
1998	A*	`conf`	Design and Implementation of the NUMAchine Multiprocessor. DAC A. Grbic, Stephen Brown, S. Caranci, R. Grindley, M. Gusat, Guy G. Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic
1997	—	`conf`	On two-step routing for FPGAS. ISPD Guy G. Lemieux, Stephen Dean Brown, Daniel Vranesic