Guy G. F. Lemieux

34 papers A 5B 6Misc 6Journal 7Unranked 10

Year	Rank	Type	Title / Venue / Authors
2023	J	`jnl`	Cache Abstraction for Data Race Detection in Heterogeneous Systems with Non-coherent Accelerators. ACM Trans. Embed. Comput. Syst. May Young, Alan J. Hu, Guy G. F. Lemieux
2023	J	`jnl`	MEDUSA: A Multi-Resolution Machine Learning Congestion Estimation Method for 2D and 3D Global Routing. ACM Trans. Design Autom. Electr. Syst. Zhonghua Zhou, Yuxuan Pan, Guy G. F. Lemieux, André Ivanov
2021	B	`conf`	Cache abstraction for data race detection in heterogeneous systems with non-coherent accelerators. LCTES May Young, Alan J. Hu, Guy G. F. Lemieux
2019	B	`conf`	Low-Level Loop Analysis and Pipelining of Applications Mapped to Xilinx FPGAs. FPL Hossein Omidian, Guy G. F. Lemieux
2019	—	`conf`	Software-based Dynamic Overlays Require Fast, Fine-grained Partial Reconfiguration. HEART Hossein Omidian, Guy G. F. Lemieux
2019	J	`jnl`	TinBiNN: Tiny Binarized Neural Network Overlay in about 5, 000 4-LUTs and 5mW. CoRR Guy G. F. Lemieux, Joe Edwards, Joel Vandergriendt, Aaron Severance, Ryan De Iaco, Abdullah Raouf, Hussein Osman, Tom Watzka, Satwant Singh
2018	—	`conf`	An Accelerated OpenVX Overlay for Pure Software Programmers. FPT Hossein Omidian, Nick Ivanov, Guy G. F. Lemieux
2018	B	`conf`	Modular Block-RAM-Based Longest-Prefix Match Ternary Content-Addressable Memories. FPL Ameer M. S. Abdelhadi, Guy G. F. Lemieux, Lesley Shannon
2017	—	`conf`	Exploring automated space/time tradeoffs for OpenVX compute graphs. FPT Hossein Omidian, Guy G. F. Lemieux
2017	—	`conf`	Real-time object detection in software with custom vector instructions and algorithm changes. ASAP Joe Edwards, Guy G. F. Lemieux
2016	Misc	`conf`	A Multi-ported Memory Compiler Utilizing True Dual-Port BRAMs. FCCM Ameer M. S. Abdelhadi, Guy G. F. Lemieux
2016	J	`jnl`	Automated Space/Time Scaling of Streaming Task Graph. CoRR Hossein Omidian, Guy G. F. Lemieux
2016	J	`jnl`	Modular Switched Multiported SRAM-Based Memories. ACM Trans. Reconfigurable Technol. Syst. Ameer M. S. Abdelhadi, Guy G. F. Lemieux
2015	J	`jnl`	Fast and Memory-Efficient Routing Algorithms for Field Programmable Gate Arrays With Sparse Intracluster Routing Crossbars. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yehdhih Ould Mohammed Moctar, Guy G. F. Lemieux, Philip Brisk
2015	Misc	`conf`	Modular SRAM-Based Binary Content-Addressable Memories. FCCM Ameer M. S. Abdelhadi, Guy G. F. Lemieux
2015	Misc	`conf`	Rapid Overlay Builder for Xilinx FPGAs. FCCM Michael Xi Yue, Dirk Koch, Guy G. F. Lemieux
2015	A	`conf`	Wavefront Skipping using BRAMs for Conditional Algorithms on Vector Processors. FPGA Aaron Severance, Joe Edwards, Guy G. F. Lemieux
2014	—	`conf`	Deep and narrow binary content-addressable memories using FPGA-based BRAMs. FPT Ameer M. S. Abdelhadi, Guy G. F. Lemieux
2014	A	`conf`	Modular multi-ported SRAM-based memories. FPGA Ameer Abdelhadi, Guy G. F. Lemieux
2013	B	`conf`	An efficient FPGA overlay for portable custom instruction set extensions. FPL Dirk Koch, Christian Beckhoff, Guy G. F. Lemieux
2013	Misc	`conf`	Embedded supercomputing in FPGAs with the VectorBlox MXP Matrix Processor. CODES+ISSS Aaron Severance, Guy G. F. Lemieux
2013	Misc	`conf`	Safe Overclocking of Tightly Coupled CGRAs and Processor Arrays using Razor. FCCM Alexander Brant, Ameer Abdelhadi, Douglas H. H. Sim, Shao Lin Tang, Michael Xi Yue, Guy G. F. Lemieux
2013	B	`conf`	TputCache: High-frequency, multi-way cache for high-throughput FPGA applications. FPL Aaron Severance, Guy G. F. Lemieux
2012	A	`conf`	Accelerator compiler for the VENICE vector processor. FPGA Zhiduo Liu, Aaron Severance, Satnam Singh, Guy G. F. Lemieux
2012	A	`conf`	Parallel FPGA placement based on individual LUT placement (abstract only). FPGA Chris C. Wang, Guy G. F. Lemieux
2012	—	`conf`	Pipeline frequency boosting: Hiding dual-ported block RAM latency using intentional clock skew. FPT Alexander Brant, Ameer Abdelhadi, Aaron Severance, Guy G. F. Lemieux
2012	J	`jnl`	Rapid Synthesis and Simulation of Computational Circuits in an MPPA. J. Signal Process. Syst. David Grant, Graeme Smecher, Guy G. F. Lemieux, Rosemary Francis
2012	A	`conf`	Reducing the cost of floating-point mantissa alignment and normalization in FPGAs. FPGA Yehdhih Ould Mohammed Moctar, Nithin George, Hadi Parandeh-Afshar, Paolo Ienne, Guy G. F. Lemieux, Philip Brisk
2012	B	`conf`	Routing algorithms for FPGAS with sparse intra-cluster routing crossbars. FPL Yehdhih Ould Mohammed Moctar, Guy G. F. Lemieux, Philip Brisk
2012	Misc	`conf`	ZUMA: An Open FPGA Overlay Architecture. FCCM Alexander Brant, Guy G. F. Lemieux
2011	—	`conf`	Configuration Bitstream Reduction for SRAM-based FPGAs by Enumerating LUT Input Permutations. ReConFig Ameer Abdelhadi, Guy G. F. Lemieux
2011	—	`conf`	Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window Decomposition. ReConFig Jeffrey B. Goeders, Guy G. F. Lemieux, Steven J. E. Wilton
2009	—	`conf`	PGR: Period and glitch reduction via clock skew scheduling, delay padding and GlitchLess. FPT Xiao Dong, Guy G. F. Lemieux
2008	—	`conf`	PERG: A scalable FPGA-based pattern-matching engine with consolidated Bloomier filters. FPT Johnny Tsung Lin Ho, Guy G. F. Lemieux