Guy Bois - RankMe

68 papers A 5B 3C 12Misc 2Journal 20Unranked 25

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Real-Time Semantic Segmentation of Aerial Images Using an Embedded U-Net: A Comparison of CPU, GPU, and FPGA Workflows. CoRR Julien Posso, Hugo Kieffer, Nicolas Menga, Omar Hlimi, Sébastien Tarris, Hubert Guerard, Guy Bois, Matthieu Couderc, Eric Jenn
2024	—	`conf`	CoChrono: A Unified Hardware/Software Performance Analysis Tool for SoC-FPGA Codesign. NewCAS Fabien Portas, Guy Bois, Yvon Savaria
2024	—	`conf`	Real-Time Spacecraft Pose Estimation Using Mixed-Precision Quantized Neural Network on COTS Reconfigurable MPSoC. NewCAS Julien Posso, Guy Bois, Yvon Savaria
2024	J	`jnl`	Real-Time Spacecraft Pose Estimation Using Mixed-Precision Quantized Neural Network on COTS Reconfigurable MPSoC. CoRR Julien Posso, Guy Bois, Yvon Savaria
2022	C	`conf`	Mobile-URSONet: an Embeddable Neural Network for Onboard Spacecraft Pose Estimation. ISCAS Julien Posso, Guy Bois, Yvon Savaria
2022	J	`jnl`	Mobile-URSONet: an Embeddable Neural Network for Onboard Spacecraft Pose Estimation. CoRR Julien Posso, Guy Bois, Yvon Savaria
2019	J	`jnl`	Avionics Graphics Hardware Performance Prediction with Machine Learning. Sci. Program. Simon R. Girard, Vincent Legault, Guy Bois, Jean-François Boland
2016	J	`jnl`	Accuracy-aware processor customisation for fixed-point arithmetic. IET Comput. Digit. Tech. Shervin Vakili, J. M. Pierre Langlois, Guy Bois
2016	B	`conf`	Architectural exploration and implementation of an image processing chain with SpaceStudio FPL Fellipe Montero, Guy Bois, Eric Jenn, Kevin Duplantier
2016	—	`conf`	Node configuration for the Aho-Corasick algorithm in Intrusion Detection Systems. ANCS Alexsandre B. Lacroix, J. M. Pierre Langlois, François-Raymond Boyer, Antoine Gosselin, Guy Bois
2015	C	`conf`	Analysis and characterization of data energy tradeoffs: For VLSI architectural agility in C-RAN platforms. ISCAS Pascal Nsame, Guy Bois, Yvon Savaria
2015	—	`conf`	Designing customized microprocessors for fixed-point computation. AHS Shervin Vakili, J. M. Pierre Langlois, Guy Bois
2014	—	`conf`	A data-driven energy efficient and flexible compute fabric architecture: For adaptive computing applied to ULSI of FFT. ICECS Pascal Nsame, Guy Bois, Yvon Savaria
2014	—	`conf`	Adaptive real-time DSP acceleration for SoC applications. MWSCAS Pascal Nsame, Guy Bois, Yvon Savaria
2014	—	`conf`	Design and Test of Adaptive Computing Fabrics for Scalable and High-Efficiency Cognitive SoC Applications. NATW Pascal Nsame, Guy Bois, Yvon Savaria
2013	J	`jnl`	Customised soft processor design: a compromise between architecture description languages and parameterisable processors. IET Comput. Digit. Tech. Shervin Vakili, J. M. Pierre Langlois, Guy Bois
2013	J	`jnl`	Enhanced Precision Analysis for Accuracy-Aware Bit-Width Optimization Using Affine Arithmetic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shervin Vakili, J. M. Pierre Langlois, Guy Bois
2013	Misc	`conf`	Finite-precision error modeling using affine arithmetic. ICASSP Shervin Vakili, J. M. Pierre Langlois, Guy Bois
2013	J	`jnl`	Reduction methods for adapting optical network on chip topologies to 3D architectures. Microprocess. Microsystems Sébastien Le Beux, Ian O'Connor, Gabriela Nicolescu, Guy Bois, Pierre G. Paulin
2011	C	`conf`	A novel low-overhead flexible instrumentation framework for virtual platforms. International Symposium on Rapid System Prototyping Tennessee Carmel-Veilleux, Jean-François Boland, Guy Bois
2011	—	`conf`	Customized embedded processor design for global photographic tone mapping. ICECS Shervin Vakili, Diana Carolina Gil, J. M. Pierre Langlois, Yvon Savaria, Guy Bois
2011	A	`conf`	Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology. DATE Sébastien Le Beux, Jelena Trajkovic, Ian O'Connor, Gabriela Nicolescu, Guy Bois, Pierre G. Paulin
2010	C	`conf`	A system-level exploration flow for optica network on chip (ONoC) in 3D MPSoC. ISCAS Sébastien Le Beux, Gabriela Nicolescu, Guy Bois, Pierre G. Paulin
2010	J	`jnl`	Combining mapping and partitioning exploration for NoC-based embedded systems. J. Syst. Archit. Sébastien Le Beux, Guy Bois, Gabriela Nicolescu, Youcef Bouchebaba, Michel Langevin, Pierre G. Paulin
2010	C	`conf`	IP characterization methodology for fast and accurate power consumption estimation at transactional level model. ICCD Michel Rogers-Vallée, Marc-André Cantin, Laurent Moss, Guy Bois
2010	J	`jnl`	Multi-Optical Network-on-Chip for Large Scale MPSoC. IEEE Embed. Syst. Lett. Sébastien Le Beux, Jelena Trajkovic, Ian O'Connor, Gabriela Nicolescu, Guy Bois, Pierre G. Paulin
2009	J	`jnl`	High Acceleration for Video Processing Applications Using Specialized Instruction Set Based on Parallelism and Data Reuse. J. Signal Process. Syst. Nicolas Beucher, Normand Bélanger, Yvon Savaria, Guy Bois
2009	J	`jnl`	Integrating Abstraction Techniques for Formal Verification of Analog Designs. J. Aerosp. Comput. Inf. Commun. Mohamed H. Zaki, William Denman, Sofiène Tahar, Guy Bois
2009	—	`conf`	Optimizing Configuration and Application Mapping for MPSoC Architectures. AHS Sébastien Le Beux, Gabriela Nicolescu, Guy Bois, Youcef Bouchebaba, Michel Langevin, Pierre G. Paulin
2009	J	`jnl`	Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories. Trans. High Perform. Embed. Archit. Compil. Patrick Mahoney, Yvon Savaria, Guy Bois, Patrice Plante
2008	C	`conf`	Acceleration of a 3D target tracking algorithm using an application specific instruction set processor. ICCD Sebastien Fontaine, Sylvain Goyette, J. M. Pierre Langlois, Guy Bois
2008	C	`conf`	Automation of Communication Refinement and Hardware Synthesis within a System-Level Design Methodology. IEEE International Workshop on Rapid System Prototyping Laurent Moss, Marc-André Cantin, Guy Bois, El Mostapha Aboulhamid
2008	C	`conf`	Exploring ISS Abstractions for Embedded Software Design. DSD Sebastien Fontaine, Luc Filion, Guy Bois
2008	J	`jnl`	Formal verification of analog and mixed signal designs: A survey. Microelectron. J. Mohamed H. Zaki, Sofiène Tahar, Guy Bois
2007	—	`conf`	A Methodology to Evaluate the Energy Efficiency of Application Specific Processors. ICECS Nicolas Beucher, Normand Bélanger, Yvon Savaria, Guy Bois
2007	—	`conf`	An FPGA Implementation of a Scalable Network-on-Chip Based on the Token Ring Concept. ICECS Karim Hadjiat, Francis St-Pierre, Guy Bois, Yvon Savaria, Michel Langevin, Pierre G. Paulin
2007	B	`conf`	Combining Symbolic Simulation and Interval Arithmetic for the Verification of AMS Designs. FMCAD Mohamed H. Zaki, Ghiath Al Sammane, Sofiène Tahar, Guy Bois
2007	—	`conf`	Communication Structure Refinement using Temporal Constraints Analysis. ICECS Alena Tsikhanovich, El Mostapha Aboulhamid, Guy Bois
2007	C	`conf`	Qualitative Abstraction based Verification for Analog Circuits. ISoLA Mohamed H. Zaki, Sofiène Tahar, Guy Bois
2007	A	`conf`	Seamless hardware/software performance co-monitoring in a codesign simulation environment with RTOS support. DATE Laurent Moss, Maxime de Nanclas, Luc Filion, Sebastien Fontaine, Guy Bois, El Mostapha Aboulhamid
2006	J	`jnl`	A SystemC Refinement Methodology for Embedded Software. IEEE Des. Test Comput. Jérôme Chevalier, Maxime de Nanclas, Luc Filion, Olivier Benny, Mathieu Rondonneau, Guy Bois, El Mostapha Aboulhamid
2006	—	`conf`	A practical approach for monitoring analog circuits. ACM Great Lakes Symposium on VLSI Mohamed H. Zaki, Sofiène Tahar, Guy Bois
2006	—	`conf`	Integration of Configurable Processors in a Multiprocessor Platform. SoCC Simon Provost, Bruno Lavigueur, Guy Bois, Gabriela Nicolescu
2006	—	`conf`	Motion Compensated Frame Rate Conversion Using a Specialized Instruction Set Processor. SiPS Nicolas Beucher, Normand Bélanger, Yvon Savaria, Guy Bois
2006	—	`conf`	Transaction Level Modeling in Hardware/Software System Design using .Net Framework. CCECE Alena Tsikhanovich, Frédéric Rousseau, El Mostapha Aboulhamid, Guy Bois
2005	—	`conf`	A Methodology for Hw/Sw Specification and Simulation at Multiple Levels of Abstraction. IWSOC Alena Tsikhanovich, El Mostapha Aboulhamid, Guy Bois
2005	—	`conf`	A Reprogrammable SoC Design for a Real-Time Control Application. MSE Jean-Francois Thibeault, Mortimer Hubin, François Deslauriers, Patrick Samson, Guy Bois
2004	A	`conf`	.NET Framework - A Solution for the Next Generation Tools for System-Level Modeling and Simulation. DATE James Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu, Luc Charest, François R. Boyer, J. P. David, Guy Bois
2004	A	`conf`	A System Level Exploration Platform and Methodology for Network Applications Based on Configurable Processors. DATE D. Quinn, Bruno Lavigueur, Guy Bois, El Mostapha Aboulhamid
2004	B	`conf`	ESys.Net: a new solution for embedded systems modeling and simulation. LCTES James Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu, Luc Charest, François R. Boyer, J. P. David, Guy Bois
2004	—	`conf`	Using Design Patterns for Type Unification and Introspection in SystemC. IWSOC Luc Charest, El Mostapha Aboulhamid, Guy Bois
2004	—	`conf`	Verification Strategy Determination Using Dependence Analysis of Transaction-Level Models. IWSOC S. Regimbal, Yvon Savaria, Guy Bois
2003	C	`conf`	A methodology for the design of AHB bus master wrappers. DSD Marc Bertola, Guy Bois
2003	—	`ch.`	Applying Multi-Paradigm and Design Pattern Approaches to Hardware/Software Design and Reuse. Patterns and Skeletons for Parallel and Distributed Computing Luc Charest, El Mostapha Aboulhamid, Guy Bois
2003	—	`conf`	Automating Functional Coverage Analysis Based on an Executable Specification. IWSOC S. Regimbal, Jean-Francois Lemire, Yvon Savaria, Guy Bois, El Mostapha Aboulhamid, A. Baron
2003	C	`conf`	SPACE: A Hardware/Software SystemC Modeling Platform Including an RTOS. FDL Jérôme Chevalier, Mathieu Rondonneau, Olivier Benny, Guy Bois, El Mostapha Aboulhamid, François R. Boyer
2003	—	`conf`	Teaching Bus Architectures with a Basic, Hands-On SOC Platform. MSE Marc Bertola, Guy Bois
2001	A	`conf`	A methodology for interfacing open source systemC with a third party software. DATE Luc Charest, Michel Reid, El Mostapha Aboulhamid, Guy Bois
2001	—	`conf`	Minimizing process-induced skew using delay tuning. ISCAS (4) Mohamed Nekili, Yvon Savaria, Guy Bois
1999	—	`conf`	Development of a high performance TSPC library for implementation of large digital building blocks. ISCAS (1) B. Le Chapelain, A. Mechain, Yvon Savaria, Guy Bois
1999	J	`jnl`	Reconfigurable pipelined 2-D convolvers for fast digital signal processing. IEEE Trans. Very Large Scale Integr. Syst. B. Bosi, Guy Bois, Yvon Savaria
1999	J	`jnl`	Spatial characterization of process variations via MOS transistor time constants in VLSI and WSI. IEEE J. Solid State Circuits Mohamed Nekili, Yvon Savaria, Guy Bois
1998	—	`conf`	Design of Clock Distribution Networks in Presence of Process Variations. Great Lakes Symposium on VLSI Mohamed Nekili, Yvon Savaria, Guy Bois
1998	Misc	`conf`	Self Sorting Radix_2 FFT on FPGA using Parallel Pipelined Distributed Arithmetic Blocks. FCCM Manoucher Shaditalab, Guy Bois, Mohamad Sawan
1997	J	`jnl`	Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations. IEEE Trans. Very Large Scale Integr. Syst. Mohamed Nekili, Guy Bois, Yvon Savaria
1996	J	`jnl`	Efficient generation of diagonal constraints for 2-D mask compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Guy Bois, Eduard Cerny
1994	C	`conf`	A Fast Low-Power Driver for Long Interconnections in VLSI Systems. ISCAS Mohamed Nekili, Yvon Savaria, Guy Bois
1988	J	`jnl`	Built-in self-test of a CMOS ALU. IEEE Des. Test Eduard Cerny, El Mostapha Aboulhamid, Guy Bois, Jocelyn Cloutier