Gustavo Sutter

36 papers B 10Journal 13Unranked 12

Year	Rank	Type	Title / Venue / Authors
2023	J	`jnl`	Enhancing Conditional Stalling to Boost Performance of Stream-Processing Logic With RAW Dependencies. IEEE Trans. Circuits Syst. II Express Briefs Tobias Alonso, Gustavo Sutter, Sergio López-Buedo, Jorge E. López de Vergara
2021	J	`jnl`	LOCO-ANS: An Optimization of JPEG-LS Using an Efficient and Low-Complexity Coder Based on ANS. IEEE Access Tobias Alonso, Gustavo Sutter, Jorge E. López de Vergara
2019	B	`conf`	Limago: An FPGA-Based Open-Source 100 GbE TCP/IP Stack. FPL Mario Ruiz, David Sidler, Gustavo Sutter, Gustavo Alonso, Sergio López-Buedo
2019	J	`jnl`	Radix-10 decimal logarithm by direct selection for 6-input LUTs programmable devices. Microprocess. Microsystems Martín Vázquez, Lucas Leiva, Gustavo Sutter
2018	—	`conf`	FPGA-based TCP/IP Checksum Offloading Engine for 100 Gbps Networks. ReConFig Gustavo Sutter, Mario Ruiz, Sergio López-Buedo, Gustavo Alonso
2018	B	`conf`	Submicrosecond Latency Video Compression in a Low-End FPGA-based System-on-Chip. FPL Tobias Alonso, Mario Ruiz, Angel Lopez Garcia-Arias, Gustavo Sutter, Jorge E. López de Vergara
2017	—	`conf`	A single-FPGA architecture for detecting heavy hitters in 100 Gbit/s ethernet links. ReConFig Jose Fernando Zazo, Sergio López-Buedo, Mario Ruiz, Gustavo Sutter
2017	—	`conf`	An FPGA-based approach for packet deduplication in 100 gigabit-per-second networks. ReConFig Mario Ruiz, Gustavo Sutter, Sergio López-Buedo, Jose Fernando Zazo, Jorge E. López de Vergara
2016	J	`jnl`	Accurate and affordable packet-train testing systems for multi-gigabit-per-second networks. IEEE Commun. Mag. Mario Ruiz, Javier Ramos, Gustavo Sutter, Jorge E. López de Vergara, Sergio López-Buedo, Javier Aracil
2016	—	`conf`	Automated synthesis of FPGA-based packet filters for 100 Gbps network monitoring applications. ReConFig Jose Fernando Zazo, Sergio López-Buedo, Gustavo Sutter, Javier Aracil
2016	—	`conf`	FPGA-based encrypted network traffic identification at 100 Gbit/s. ReConFig Mario Ruiz, Gustavo Sutter, Sergio López-Buedo, Jorge E. López de Vergara
2016	B	`conf`	Harnessing Programmable SoCs to develop cost-effective network quality monitoring devices. FPL Mario Ruiz, Javier Ramos, Gustavo Sutter, Sergio López-Buedo, Jorge E. López de Vergara, C. Sisterna
2015	—	`conf`	Leveraging open source platforms and high-level synthesis for the design of FPGA-based 10 GbE active network probes. ReConFig Mario Ruiz, Gustavo Sutter, Sergio López-Buedo, Javier Ramos, Jorge E. López de Vergara, Javier Aracil
2014	J	`jnl`	Bridging the gap between hardware and software open source network developments. IEEE Netw. Marco Forconesi, Gustavo Sutter, Sergio López-Buedo, Jorge E. López de Vergara, Javier Aracil
2014	—	`conf`	TNT10G: A high-accuracy 10 GbE traffic player and recorder for multi-Terabyte traces. ReConFig Jose Fernando Zazo, Marco Forconesi, Sergio López-Buedo, Gustavo Sutter, Javier Aracil
2013	B	`conf`	Accurate and flexible flow-based monitoring for high-speed networks. FPL Marco Forconesi, Gustavo Sutter, Sergio López-Buedo, Javier Aracil
2013	J	`jnl`	Efficient Elliptic Curve Point Multiplication Using Digit-Serial Binary Field Operations. IEEE Trans. Ind. Electron. Gustavo Sutter, Jean-Pierre Deschamps, José Luis Imaña
2013	J	`jnl`	FPGA acceleration using high-level languages of a Monte-Carlo method for pricing complex options. J. Syst. Archit. Diego Sanchez-Roman, Victor Moreno, Sergio López-Buedo, Gustavo Sutter, Iván González, Francisco J. Gomez-Arribas, Javier Aracil
2012	—	`book`	Guide to FPGA Implementation of Arithmetic Functions Jean-Pierre Deschamps, Gustavo Sutter, Enrique Cantó
2012	J	`jnl`	Virtualization of reconfigurable coprocessors in HPRC systems with multicore architecture. J. Syst. Archit. Iván González, Sergio López-Buedo, Gustavo Sutter, Diego Sanchez-Roman, Francisco J. Gomez-Arribas, Javier Aracil
2011	J	`jnl`	High-Level Languages and Floating-Point Arithmetic for FPGA-Based CFD Simulations. IEEE Des. Test Comput. Diego Sanchez-Roman, Gustavo Sutter, Sergio López-Buedo, Iván González, Francisco J. Gomez-Arribas, Javier Aracil, Francisco Palacios
2011	J	`jnl`	Modular Multiplication and Exponentiation Architectures for Fast RSA Cryptosystem Based on Digit Serial Computation. IEEE Trans. Ind. Electron. Gustavo Sutter, Jean-Pierre Deschamps, José Luis Imaña
2011	J	`jnl`	Selected Papers from the Southern Programmable Logic Conference (SPL2010). Int. J. Reconfigurable Comput. Elias Todorovich, Gustavo Sutter
2010	B	`conf`	Efficient FPGA Modular Multiplication and Exponentiation Architectures Using Digit Serial Computation. FPL Gustavo Sutter, Jean-Pierre Deschamps, José Luis Imaña
2010	J	`jnl`	High-Speed FPGA 10's Complement Adders-Subtractors. Int. J. Reconfigurable Comput. Gery Bioul, Martín Vázquez, Jean-Pierre Deschamps, Gustavo Sutter
2009	—	`conf`	A FPGA IEEE-754-2008 Decimal64 Floating-Point Multiplier. ReConFig Carlos Minchola, Gustavo Sutter
2009	—	`conf`	Decimal Adders/Subtractors in FPGA: Efficient 6-input LUT Implementations. ReConFig Martín Vázquez, Gustavo Sutter, Gery Bioul, Jean-Pierre Deschamps
2009	—	`conf`	FPGA Implementations of BCD Multipliers. ReConFig Gustavo Sutter, Elias Todorovich, Gery Bioul, Martín Vázquez, Jean-Pierre Deschamps
2009	B	`conf`	High speed fixed point dividers for FPGAs. FPL Gustavo Sutter, Jean-Pierre Deschamps
2008	J	`jnl`	Selected Papers from SPL 2008: Programmable Logic and Applications. Int. J. Reconfigurable Comput. Gustavo Sutter, Richard Katz
2005	B	`conf`	Finite Field Division Implementation. FPL Jean-Pierre Deschamps, Gustavo Sutter
2004	B	`conf`	Comparative Study of SRT-Dividers in FPGA. FPL Gustavo Sutter, Gery Bioul, Jean-Pierre Deschamps
2004	—	`conf`	Power Aware Dividers in FPGA. PATMOS Gustavo Sutter, Jean-Pierre Deschamps, Gery Bioul, Eduardo I. Boemo
2002	B	`conf`	A Tool for Activity Estimation in FPGAs. FPL Elias Todorovich, M. Gilabert, Gustavo Sutter, Sergio López-Buedo, Eduardo I. Boemo
2002	B	`conf`	FSM Decomposition for Low Power in FPGA. FPL Gustavo Sutter, Elias Todorovich, Sergio López-Buedo, Eduardo I. Boemo
2002	—	`conf`	Low-Power FSMs in FPGA: Encoding Alternatives. PATMOS Gustavo Sutter, Elias Todorovich, Sergio López-Buedo, Eduardo I. Boemo