Gustavo E. Téllez

22 papers A* 4A 3C 1Journal 9Unranked 5
YearRankTypeTitle / Venue / Authors
2022 — conf
LEO: Line End Optimizer for Sub-7nm Technology Nodes.
ISPD
Diwesh Pandey, Gustavo E. Téllez, James Leland
2020 A* conf
Latch Clustering for Timing-Power Co-Optimization.
DAC
Chau-Chin Huang, Gustavo E. Téllez, Gi-Joon Nam, Yao-Wen Chang
2020 A conf
Self-Aligned Double-Patterning Aware Legalization.
DATE
Hua Xiang, Gi-Joon Nam, Gustavo E. Téllez, Shyam Ramji, Xiaoqing Xu
2018 — conf
Interconnect Optimization Considering Multiple Critical Paths.
ISPD
Jiang Hu, Ying Zhou, Yaoguang Wei, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Téllez, Gi-Joon Nam
2018 — conf
On Coloring and Colorability Analysis of Integrated Circuits with Triple and Quadruple Patterning Techniques.
ISPD
Alexey Lvov, Gustavo E. Téllez, Gi-Joon Nam
2015 J jnl
Detailed Routing Algorithms for Advanced Technology Nodes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Markus Ahrens, Michael Gester, Niko Klewinghaus, Dirk Müller, Sven Peyer, Christian Schulte, Gustavo E. Téllez
2014 J jnl
Techniques for scalable and effective routability evaluation.
ACM Trans. Design Autom. Electr. Syst.
Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar
2012 A* conf
GLARE: global and local wiring aware routability evaluation.
DAC
Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar
2011 J jnl
Design methodology for the IBM POWER7 microprocessor.
IBM J. Res. Dev.
Joshua Friedrich, Ruchir Puri, Uwe Brandt, Markus Bühler, Jack DiLullo, Jeremy Hopkins, Mozammel Hossain, Michael A. Kazda, Joachim Keinert, Zahi M. Kurzum, Douglass Lamb, Alice Lee, Frank Musante, Jens Noack, Peter J. Osler, Stephen D. Posluszny, Haifeng Qian, Shyam Ramji, Vasant B. Rao, Lakshmi N. Reddy, Haoxing Ren, Thomas E. Rosser, Benjamin R. Russell, Cliff C. N. Sze, Gustavo E. Téllez
2010 — conf
What makes a design difficult to route.
ISPD
Charles J. Alpert, Zhuo Li, Michael D. Moffitt, Gi-Joon Nam, Jarrod A. Roy, Gustavo E. Téllez
2001 J jnl
Activity-driven clock design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Amir H. Farrahi, Chunhong Chen, Ankur Srivastava, Gustavo E. Téllez, Majid Sarrafzadeh
2000 J jnl
EDA in IBM: past, present, and future.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
John A. Darringer, Evan E. Davidson, David J. Hathaway, Bernd Koenemann, Mark A. Lavin, Joseph K. Morrell, Khalid Rahmat, Wolfgang Roesner, Erich C. Schanzenbach, Gustavo E. Téllez, Louise Trevillyan
1998 J jnl
Exploiting Sleep Mode for Memory Partitioning and Other Applications.
VLSI Design
Amir H. Farrahi, Gustavo E. Téllez, Majid Sarrafzadeh
1998 J jnl
On Rectilinear Distance-Preserving Trees.
VLSI Design
Gustavo E. Téllez, Majid Sarrafzadeh
1997 — conf
A VLSI artwork legalization technique based on a new criterion of minimum layout perturbation.
ISPD
Fook-Luen Heng, Zhan Chen, Gustavo E. Téllez
1997 J jnl
A delay budgeting algorithm ensuring maximum flexibility in placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Majid Sarrafzadeh, David A. Knol, Gustavo E. Téllez
1997 J jnl
Minimal buffer insertion in clock trees with skew and slew rate constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Gustavo E. Téllez, Majid Sarrafzadeh
1997 A* conf
Unification of Budgeting and Placement.
DAC
Majid Sarrafzadeh, David A. Knol, Gustavo E. Téllez
1995 A conf
Activity-driven clock design for low power circuits.
ICCAD
Gustavo E. Téllez, Amir H. Farrahi, Majid Sarrafzadeh
1995 A* conf
Memory Segmentation to Exploit Sleep Mode Operation.
DAC
Amir H. Farrahi, Gustavo E. Téllez, Majid Sarrafzadeh
1995 C conf
On Rectilinear Distance-Preserving Trees.
ISCAS
Gustavo E. Téllez, Majid Sarrafzadeh
1994 A conf
Clock period constrained minimal buffer insertion in clock trees.
ICCAD
Gustavo E. Téllez, Majid Sarrafzadeh