Gurindar S. Sohi

111 papers A* 61A 5B 4C 1Misc 2Journal 25Unranked 9

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	A Non-Traditional Approach to Assisting Data Address Translation. CoRR Shyam Murthy, Gurindar S. Sohi
2021	A*	`conf`	Fat Loads: Exploiting Locality Amongst Contemporaneous Load Operations to Optimize Cache Accesses. MICRO Vanshika Baoni, Adarsh Mittal, Gurindar S. Sohi
2018	A*	`conf`	Filtering Translation Bandwidth with Virtual Caching. ASPLOS Hongil Yoon, Jason Lowe-Power, Gurindar S. Sohi
2017	A	`conf`	ATM: Approximate Task Memoization in the Runtime System. IPDPS Iulian Brumar, Marc Casas, Miquel Moretó, Mateo Valero, Gurindar S. Sohi
2016	A*	`conf`	Revisiting virtual L1 caches: A practical design using dynamic synonym remapping. HPCA Hongil Yoon, Gurindar S. Sohi
2014	A*	`conf`	Adaptive, efficient, parallel execution of parallel programs. PLDI Srinath Sridharan, Gagan Gupta, Gurindar S. Sohi
2014	—	`conf`	Author retrospective for cooperative cache partitioning for chip multiprocessors. ICS 25th Anniversary Jichuan Chang, Gurindar S. Sohi
2014	A*	`conf`	Globally precise-restartable execution of parallel programs. PLDI Gagan Gupta, Srinath Sridharan, Gurindar S. Sohi
2013	A	`conf`	Holistic run-time parallelism management for time and energy efficiency. ICS Srinath Sridharan, Gagan Gupta, Gurindar S. Sohi
2012	—	`conf`	Efficient, precise-restartable program execution on future multicores. Hot Chips Symposium Gagan Gupta, Srinath Sridharan, Gurindar S. Sohi
2012	J	`jnl`	Supporting Overcommitted Virtual Machines through Hardware Spin Detection. IEEE Trans. Parallel Distributed Syst. Koushik Chakraborty, Philip M. Wells, Gurindar S. Sohi
2011	A*	`conf`	Dataflow execution of sequential imperative programs on multicore architectures. MICRO Gagan Gupta, Gurindar S. Sohi
2009	J	`jnl`	Dynamic heterogeneity and the need for multicore virtualization. ACM SIGOPS Oper. Syst. Rev. Philip M. Wells, Koushik Chakraborty, Gurindar S. Sohi
2009	A*	`conf`	Mixed-mode multicore reliability. ASPLOS Philip M. Wells, Koushik Chakraborty, Gurindar S. Sohi
2009	B	`conf`	Serialization sets: a dynamic dependence-based parallel execution model. PPoPP Matthew D. Allen, Srinath Sridharan, Gurindar S. Sohi
2009	—	`ch.`	Speculatively Multithreaded Architectures. Multicore Processors and Systems Gurindar S. Sohi, T. N. Vijaykumar
2008	A*	`conf`	Adapting to intermittent faults in multicore systems. ASPLOS Philip M. Wells, Koushik Chakraborty, Gurindar S. Sohi
2008	A*	`conf`	Serializing instructions in system-intensive workloads: Amdahl's Law strikes again. HPCA Philip M. Wells, Gurindar S. Sohi
2007	B	`conf`	Adapting to Intermittent Faults in Future Multicore Systems. PACT Philip M. Wells, Koushik Chakraborty, Gurindar S. Sohi
2007	A	`conf`	Cooperative cache partitioning for chip multiprocessors. ICS Jichuan Chang, Gurindar S. Sohi
2006	A*	`conf`	Computation spreading: employing hardware migration to specialize CMP cores on-the-fly. ASPLOS Koushik Chakraborty, Philip M. Wells, Gurindar S. Sohi
2006	A*	`conf`	Cooperative Caching for Chip Multiprocessors. ISCA Jichuan Chang, Gurindar S. Sohi
2006	B	`conf`	Hardware support for spin management in overcommitted virtual machines. PACT Philip M. Wells, Koushik Chakraborty, Gurindar S. Sohi
2006	A*	`conf`	Program Demultiplexing: Data-flow based Speculative Parallelization of Methods in Sequential Programs. ISCA Saisanthosh Balakrishnan, Gurindar S. Sohi
2004	J	`jnl`	Characterization of Problem Stores. IEEE Comput. Archit. Lett. Allison L. Holloway, Gurindar S. Sohi
2004	A*	`conf`	Coherence decoupling: making use of incoherence. ASPLOS Jaehyuk Huh, Jichuan Chang, Doug Burger, Gurindar S. Sohi
2004	A*	`conf`	Single-Chip Multiprocessors: The Next Wave of Computer Architecture Innovation. MICRO Gurindar S. Sohi
2004	J	`jnl`	Speculative Incoherent Cache Protocols. IEEE Micro Jaehyuk Huh, Doug Burger, Jichuan Chang, Gurindar S. Sohi
2004	A*	`conf`	Use-Based Register Caching with Decoupled Indexing. ISCA J. Adam Butts, Gurindar S. Sohi
2003	A*	`conf`	Exploiting Value Locality in Physical Register Files. MICRO Saisanthosh Balakrishnan, Gurindar S. Sohi
2003	A*	`conf`	Parallelism in the Front-End. ISCA Paramjit S. Oberoi, Gurindar S. Sohi
2002	A*	`conf`	A quantitative framework for automated pre-execution thread selection. MICRO Amir Roth, Gurindar S. Sohi
2002	A*	`conf`	Characterizing and predicting value degree of use. MICRO J. Adam Butts, Gurindar S. Sohi
2002	A*	`conf`	Dynamic dead-instruction detection and elimination. ASPLOS J. Adam Butts, Gurindar S. Sohi
2002	A*	`conf`	Master/slave speculative parallelization. MICRO Craig B. Zilles, Gurindar S. Sohi
2002	B	`conf`	Out-of-Order Instruction Fetch Using Multiple Sequencers. ICPP Paramjit S. Oberoi, Gurindar S. Sohi
2002	J	`jnl`	Reducing Memory Latency via Read-after-Read Memory Dependence Prediction. IEEE Trans. Computers Andreas Moshovos, Gurindar S. Sohi
2001	A*	`conf`	A Programmable Co-Processor for Profiling. HPCA Craig B. Zilles, Gurindar S. Sohi
2001	A*	`conf`	Execution-based prediction using speculative slices. ISCA Craig B. Zilles, Gurindar S. Sohi
2001	J	`jnl`	Microarchitectural innovations: boosting microprocessor performance beyond semiconductor technology scaling. Proc. IEEE Andreas Moshovos, Gurindar S. Sohi
2001	Misc	`conf`	Microprocessors - 10 Years Back, 10 Years Ahead. Informatics Gurindar S. Sohi
2001	A*	`conf`	Speculative Data-Driven Multithreading. HPCA Amir Roth, Gurindar S. Sohi
2001	J	`jnl`	Speculative Multithreaded Processors. Computer Gurindar S. Sohi, Amir Roth
2001	J	`jnl`	Speculative Versioning Cache. IEEE Trans. Parallel Distributed Syst. T. N. Vijaykumar, Sridhar Gopal, James E. Smith, Gurindar S. Sohi
2001	J	`jnl`	Squash Reuse via a Simplified Implementation of Register Integration. J. Instr. Level Parallelism Amir Roth, Gurindar S. Sohi
2000	A*	`conf`	A static power model for architects. MICRO J. Adam Butts, Gurindar S. Sohi
2000	Misc	`conf`	Amir Roth: Speculative Multithreaded Processors. HiPC Gurindar S. Sohi
2000	J	`jnl`	Memory Dependence Prediction in Multimedia Applications. J. Instr. Level Parallelism Andreas Moshovos, Gurindar S. Sohi
2000	A*	`conf`	Memory Dependence Speculation Tradeoffs in Centralized, Continuous-Window Superscalar Processors. HPCA Andreas Moshovos, Gurindar S. Sohi
2000	A*	`conf`	Register integration: a simple and efficient implementation of squash reuse. MICRO Amir Roth, Gurindar S. Sohi
2000	A*	`conf`	Understanding the backward slices of performance degrading instructions. ISCA Craig B. Zilles, Gurindar S. Sohi
1999	A*	`conf`	Effective Jump-Pointer Prefetching for Linked Data Structures. ISCA Amir Roth, Gurindar S. Sohi
1999	A	`conf`	Improving virtual function call target prediction via dependence-based pre-computation. International Conference on Supercomputing Amir Roth, Andreas Moshovos, Gurindar S. Sohi
1999	A*	`conf`	Read-After-Read Memory Dependence Prediction. MICRO Andreas Moshovos, Gurindar S. Sohi
1999	J	`jnl`	Speculative Memory Cloaking and Bypassing. Int. J. Parallel Program. Andreas Moshovos, Gurindar S. Sohi
1999	J	`jnl`	Task Selection for the Multiscalar Architecture. J. Parallel Distributed Comput. T. N. Vijaykumar, Gurindar S. Sohi
1999	A*	`conf`	The Use of Multithreading for Exception Handling. MICRO Craig B. Zilles, Joel S. Emer, Gurindar S. Sohi
1998	—	`ed.`	25 Years of the International Symposia on Computer Architecture (Selected Papers). ISCA Selected Papers Gurindar S. Sohi
1998	A*	`conf`	An Empirical Analysis of Instruction Repetition. ASPLOS Avinash Sodani, Gurindar S. Sohi
1998	A*	`conf`	Dependance Based Prefetching for Linked Data Structures. ASPLOS Amir Roth, Andreas Moshovos, Gurindar S. Sohi
1998	—	`conf`	Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors. 25 Years ISCA: Retrospectives and Reprints Gurindar S. Sohi, Sriram Vajapeyam
1998	—	`conf`	Multiscalar Processors. 25 Years ISCA: Retrospectives and Reprints Gurindar S. Sohi, Scott E. Breach, T. N. Vijaykumar
1998	A*	`ed.`	Proceedings of the 25th Annual International Symposium on Computer Architecture, ISCA 1998, Barcelona, Spain, June 27 - July 1, 1998 ISCA Mateo Valero, Gurindar S. Sohi, Doug DeGroot
1998	—	`conf`	Retrospective: Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors. 25 Years ISCA: Retrospectives and Reprints Gurindar S. Sohi
1998	—	`conf`	Retrospective: Multiscalar Processors. 25 Years ISCA: Retrospectives and Reprints Gurindar S. Sohi
1998	A*	`conf`	Speculative Versioning Cache. HPCA Sridhar Gopal, T. N. Vijaykumar, James E. Smith, Gurindar S. Sohi
1998	A*	`conf`	Task Selection for a Multiscalar Processor. MICRO T. N. Vijaykumar, Gurindar S. Sohi
1998	A*	`conf`	Understanding the Differences Between Value Prediction and Instruction Reuse. MICRO Avinash Sodani, Gurindar S. Sohi
1997	A*	`conf`	Dynamic Instruction Reuse. ISCA Avinash Sodani, Gurindar S. Sohi
1997	A*	`conf`	Dynamic Speculation and Synchronization of Data Dependences. ISCA Andreas Moshovos, Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi
1997	—	`ch.`	Memory Systems. The Computer Science and Engineering Handbook Doug Burger, James R. Goodman, Gurindar S. Sohi
1997	A*	`conf`	Streamlining Inter-Operation Memory Communication via Data Dependence Prediction. MICRO Andreas Moshovos, Gurindar S. Sohi
1996	J	`jnl`	ARB: A Hardware Mechanism for Dynamic Reordering of Memory References. IEEE Trans. Computers Manoj Franklin, Gurindar S. Sohi
1996	A*	`conf`	High-Bandwidth Address Translation for Multiple-Issue Processors. ISCA Todd M. Austin, Gurindar S. Sohi
1995	A*	`conf`	Multiscalar Processors. ISCA Gurindar S. Sohi, Scott E. Breach, T. N. Vijaykumar
1995	A*	`conf`	Streamlining Data Cache Access with Fast Address Calculation. ISCA Todd M. Austin, Dionisios N. Pnevmatikatos, Gurindar S. Sohi
1995	J	`jnl`	The microarchitecture of superscalar processors. Proc. IEEE James E. Smith, Gurindar S. Sohi
1995	A*	`conf`	Zero-cycle loads: microarchitecture support for reducing load latency. MICRO Todd M. Austin, Gurindar S. Sohi
1994	A*	`conf`	Efficient Detection of All Pointer and Array Access Errors. PLDI Todd M. Austin, Scott E. Breach, Gurindar S. Sohi
1994	A*	`conf`	Guarded Executing and Branch Prediction in Dynamic ILP Processors. ISCA Dionisios N. Pnevmatikatos, Gurindar S. Sohi
1994	J	`jnl`	Request Combining in Multiprocessors with Arbitrary Interconnection Networks. IEEE Trans. Parallel Distributed Syst. Alvin R. Lebeck, Gurindar S. Sohi
1994	A*	`conf`	The anatomy of the register file in a multiscalar processor. MICRO Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi
1993	A*	`conf`	Control flow prediction for dynamic ILP processors. MICRO Dionisios N. Pnevmatikatos, Manoj Franklin, Gurindar S. Sohi
1993	J	`jnl`	High-Bandwidth Interleaved Memories for Vector Processors-A Simulation Study. IEEE Trans. Computers Gurindar S. Sohi
1992	A*	`conf`	Dynamic Dependency Analysis of Ordinary Programs. ISCA Todd M. Austin, Gurindar S. Sohi
1992	J	`jnl`	Evaluating Design Choices for Shared Bus Multiprocessors in a Throughput-Oriented Environment. IEEE Trans. Computers MenChow Chiang, Gurindar S. Sohi
1992	A*	`conf`	Register traffic analysis for streamlining inter-operation communication in fine-grain parallel processors. MICRO Manoj Franklin, Gurindar S. Sohi
1992	A*	`conf`	The Expandable Split Window Paradigm for Exploiting Fine-Grain Parallelism. ISCA Manoj Franklin, Gurindar S. Sohi
1991	A*	`conf`	An Empirical Study of the CRAY Y-MP Processor Using the Perfect Club Benchmarks. ISCA Sriram Vajapeyam, Gurindar S. Sohi, Wei-Chung Hsu
1991	A*	`conf`	Experience with Mean Value Analysis Models for Evaluating Shared Bus, Throughput-Oriented Multiprocessors. SIGMETRICS MenChow Chiang, Gurindar S. Sohi
1991	A*	`conf`	High-Bandwidth Data Memory Systems for Superscalar Processors. ASPLOS Gurindar S. Sohi, Manoj Franklin
1990	J	`jnl`	Design and Analysis of a Gracefully Degrading Interleaved Memory System. IEEE Trans. Computers Kifung C. Cheung, Gurindar S. Sohi, Kewal K. Saluja, Dhiraj K. Pradhan
1990	C	`conf`	Exploitation of operation-level parallelism in a processor of the CRAY X-MP. ICCD Sriram Vajapeyam, Gurindar S. Sohi, Wei-Chung Hsu
1990	J	`jnl`	Instruction Issue Logic for High-Performance Interruptible, Multiple Functional Unit, Pipelines Computers. IEEE Trans. Computers Gurindar S. Sohi
1990	J	`jnl`	Scalable Shared-Memory Multiprocessor Architectures. Computer Shreekant S. Thakkar, Michel Dubois, Anthony T. Laundrie, Gurindar S. Sohi, David V. James, Stein Gjessing, Manu Thapar, Bruce Delagi, Michael J. Carlton, Alvin M. Despain
1990	J	`jnl`	The Use of Feedback in Multiprocessors and Its Application to Tree Saturation Control. IEEE Trans. Parallel Distributed Syst. Steven L. Scott, Gurindar S. Sohi
1990	J	`jnl`	The use of intermediate memories for low-latency memory access in supercomputer scalar units. J. Supercomput. Gurindar S. Sohi, Wei-Chung Hsu
1989	—	`conf`	A study of time-redundant fault tolerance techniques for high-performance pipelined computers. FTCS Gurindar S. Sohi, Manoj Franklin, Kewal K. Saluja
1989	J	`jnl`	Cache Memory Organization to Enhance the Yield of High-Performance VLSI Processors. IEEE Trans. Computers Gurindar S. Sohi
1989	—	`conf`	On the Adequacy of Direct Mapped Caches for Lisp and Prolog Data Reference Patterns. NACLP V. S. Madan, C.-J. Peng, Gurindar S. Sohi
1989	J	`jnl`	Performance Analysis of Hierarchical Cache-Consistent Multiprocessors. Perform. Evaluation Mary K. Vernon, Rajeev Jog, Gurindar S. Sohi
1989	A	`conf`	Restricted Fetch&Phi operations for parallel processing. ICS Gurindar S. Sohi, James E. Smith, James R. Goodman
1989	A*	`conf`	Tradeoffs in Instruction Format Design for Horizontal Architectures. ASPLOS Gurindar S. Sohi, Sriram Vajapeyam
1989	A*	`conf`	Using Feedback to Control Tree Saturation in Multistage Interconnection Networks. ISCA Steven L. Scott, Gurindar S. Sohi
1988	A*	`conf`	Multiple instruction issue and single-chip processors. MICRO Andrew R. Pleszkun, Gurindar S. Sohi
1988	A*	`conf`	The Performance Potential of Multiple Functional Unit Processors. ISCA Andrew R. Pleszkun, Gurindar S. Sohi
1987	A*	`conf`	Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors. ISCA Gurindar S. Sohi, Sriram Vajapeyam
1987	A*	`conf`	Organization and Analysis of a Gracefully-Degrading Interleaved Memory System. ISCA Kifung C. Cheung, Gurindar S. Sohi, Kewal K. Saluja, Dhiraj K. Pradhan
1986	—	`conf`	Features of the Structured Memory Access (SMA) Architecture. COMPCON Andrew R. Pleszkun, Gurindar S. Sohi, Bassam Z. Kahhaleh, Edward S. Davidson
1985	A*	`conf`	An Efficient LISP-Execution Architecture with a New Representation for List Structures. ISCA Gurindar S. Sohi, Edward S. Davidson, Janak H. Patel
1985	—	`—`	Blast: A Machine Architecture for High-Speed List Processing Using Associative Tables (Traversal, Pointers) Gurindar S. Sohi