Guillermo Payá Vayá

14 papers A* 1B 2Unranked 10

Year	Rank	Type	Title / Venue / Authors
2023	—	`conf`	Radiation Tolerant Reconfigurable Hardware Architecture Design Methodology. ARC Eike Trumann, Gia Bao Thieu, Johannes Schmechel, Kirsten Weide-Zaage, Katharina Schmidt, Dorian Hagenah, Guillermo Payá Vayá
2020	—	`conf`	CereBridge: An Efficient, FPGA-based Real-Time Processing Platform for True Mobile Brain-Computer Interfaces. EMBC Marc-Nils Wahalla, Guillermo Payá Vayá, Holger Blume
2019	—	`conf`	A Coding Approach to Improve the Energy Efficiency of Approximate NoCs. ReCoSoC Amir Najafi, Lennart Bamberg, Guillermo Payá Vayá, Alberto García Ortiz
2018	A*	`conf`	Cross-layer fault-space pruning for hardware-assisted fault injection. DAC Christian Dietrich, Achim Schmider, Oskar Pusz, Guillermo Payá Vayá, Daniel Lohmann
2018	—	`conf`	Transport-Triggered Soft Cores. IPDPS Workshops Pekka Jääskeläinen, Aleksi Tervo, Guillermo Payá Vayá, Timo Viitanen, Nicolai Behmann, Jarmo Takala, Holger Blume
2017	—	`conf`	A fair comparison of adders in stochastic regime. PATMOS Ardalan Najafi, Moritz Weißbrich, Guillermo Payá Vayá, Alberto García Ortiz
2011	—	`—`	Design and analysis of a generic VLIW processor for multimedia applications. Guillermo Payá Vayá
2005	—	`conf`	RAPANUI: Rapid Prototyping for Media Processor Architecture Exploration. SAMOS Guillermo Payá Vayá, Javier Martín-Langerwerf, Peter Pirsch
2004	—	`conf`	2D-DCT on FPGA by polynomial transformation in two-dimensions. ISCAS (3) Arturo Méndez Patiño, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá
2004	—	`conf`	Architectures for ICT on FPGA. FPT Arturo Méndez Patiño, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá
2004	B	`conf`	FPGA Custom DSP for ECG Signal Analysis and Compression. FPL Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá, Ricardo José Colom-Palero, Rafael Gadea Gironés, José Belenguer
2003	—	`conf`	A new inverse discrete wavelet packet transform architecture. ISSPA (2) Guillermo Payá Vayá, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Vicente Herrero-Bosch, Joaquín Cerdá
2003	B	`conf`	Fully Parameterized Discrete Wavelet Packet Transform Architecture Oriented to FPGA. FPL Guillermo Payá Vayá, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Francisco José Mora Mas
2003	—	`conf`	Implementing a Margolus Neighborhood Cellular Automata on a FPGA. IWANN (2) Joaquín Cerdá, Rafael Gadea Gironés, Guillermo Payá Vayá