Guillermo Payá-Vayá

67 papers A 3B 3C 2Misc 1Journal 17Unranked 41

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	An Open-Source IEEE Trans. Very Large Scale Integr. Syst. Moritz Weißbrich, Adilet Dossanov, Yerzhan Kudabay, Alexander Meyer, Vadim Issakov, Guillermo Payá-Vayá
2025	J	`jnl`	DCMA: Accelerating Parallel DMA Transfers with a Multi-Port Direct Cached Memory Access in a Massive-Parallel Vector Processor. ACM Trans. Archit. Code Optim. Gia Bao Thieu, Sven Gesper, Guillermo Payá-Vayá
2025	—	`conf`	Design Space Exploration of a Direct Cached Memory Access Controller Optimized for HBM Memory Systems using TAPRE-HBM. CCMCC Gia Bao Thieu, Johannes Knödtel, Florian Rokohl, Marc Reichenbach, Guillermo Payá-Vayá
2024	—	`conf`	A 505nW Programmable NanoController in 22 nm FDSOI-CMOS for Autonomous Ultra-Low-Power Mixed-Signal SoCs. NorCAS Moritz Weißbrich, Alexander Meyer, Adilet Dossanov, Vadim Issakov, Guillermo Payá-Vayá
2024	—	`conf`	A Graph Neural Network Approach to Improve List Scheduling Heuristics Under Register-Pressure. MOCAST Fabian Stuckmann, Guillermo Payá-Vayá
2024	—	`conf`	A Novel Chaining-Based Indirect Addressing Mode in a Vertical Vector Processor. SAMOS Sven Gesper, Daniel Köhler, Gia Bao Thieu, Jasper Homann, Frank Meinl, Holger Blume, Guillermo Payá-Vayá
2024	J	`jnl`	Energy-Aware Register Allocation for VLIW Processors. J. Signal Process. Syst. Fabian Stuckmann, Moritz Weißbrich, Guillermo Payá-Vayá
2024	—	`conf`	Multi-Level Prototyping of a Vertical Vector AI Processing System. ASAP Frederik Kautz, Sven Gesper, Gia Bao Thieu, Hans-Martin Blüthgen, Holger Blume, Guillermo Payá-Vayá
2024	—	`conf`	NanoSoftController: A Minimal Soft Processor for System State Control in FPGA Systems. SAMOS Moritz Weißbrich, Germain Seidlitz, Guillermo Payá-Vayá
2023	J	`jnl`	A 4μW Low-Power Audio Processor System for Real-Time Jaw Movements Recognition in Grazing Cattle. J. Signal Process. Syst. Luciano S. Martínez Rau, Moritz Weißbrich, Guillermo Payá-Vayá
2023	—	`conf`	Exploiting Subword Permutations to Maximize CNN Compute Performance and Efficiency. ASAP Michael Beyer, Sven Gesper, Andre Guntoro, Guillermo Payá-Vayá, Holger Blume
2023	—	`conf`	N ICCE-Berlin Sven Gesper, Gia Bao Thieu, Daniel Köhler, Markus Kock, Tim Berthold, Oliver Renke, Holger Blume, Guillermo Payá-Vayá
2023	—	`conf`	PATARA: Extension of a Verification Framework for RISC-V Instruction Set Implementations. SAMOS Sven Gesper, Fabian Stuckmann, Lucy Wöbbekind, Guillermo Payá-Vayá
2023	—	`conf`	TAPRE-HBM: Trace-Based Processor Rapid Emulation Using HBM on FPGAs. ARC Johannes Knödtel, Hector Gerardo Muñoz Hernandez, Alexander Lehnert, Gia Bao Thieu, Sven Gesper, Guillermo Payá-Vayá, Marc Reichenbach
2023	A	`conf`	ZuSE Ki-Avf: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous Driving. DATE Gia Bao Thieu, Sven Gesper, Guillermo Payá-Vayá, Christoph Riggers, Oliver Renke, Till Fiedler, Jakob Marten, Tobias Stuckenberg, Holger Blume, Christian Weis, Lukas Steiner, Chirag Sudarshan, Norbert Wehn, Lennart M. Reimann, Rainer Leupers, Michael Beyer, Daniel Köhler, Alisa Jauch, Jan Micha Borrmann, Setareh Jaberansari, Tim Berthold, Meinolf Blawat, Markus Kock, Gregor Schewior, Jens Benndorf, Frederik Kautz, Hans-Martin Blüthgen, Christian Sauer
2022	—	`conf`	A Silicon-Proof Controller System for Flexible Ultra-Low-Power Energy Harvesting Platforms. MOCAST Moritz Weißbrich, Holger Blume, Guillermo Payá-Vayá
2022	J	`jnl`	A Survey on Application Specific Processor Architectures for Digital Hearing Aids. J. Signal Process. Syst. Lukas Gerlach, Guillermo Payá-Vayá, Holger Blume
2022	—	`conf`	NanoController: A Minimal and Flexible Processor Architecture for Ultra-Low-Power Always-On System State Controllers. SAMOS Moritz Weißbrich, Guillermo Payá-Vayá
2021	J	`jnl`	Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments. Int. J. Parallel Program. Sven Gesper, Moritz Weißbrich, Tobias Stuckenberg, Pekka Jääskeläinen, Holger Blume, Guillermo Payá-Vayá
2021	—	`conf`	PATARA: A REVERSI-Based Open-Source Tool for Post-Silicon Validation of Processor Cores. MOCAST Fabian Stuckmann, Pasha A. Fistanto, Guillermo Payá-Vayá
2021	—	`conf`	Using Genetic Algorithms to Optimize the Instruction-Set Encoding on Processor Cores. MOCAST Moritz Weißbrich, Javier Andrés Moreno-Medina, Guillermo Payá-Vayá
2020	—	`conf`	A Runtime-Reconfigurable Operand Masking Technique for Energy-Efficient Approximate Processor Architectures. MOCAST Moritz Weißbrich, Alberto García Ortiz, Guillermo Payá-Vayá
2020	—	`conf`	Design Space Exploration Framework for Tensilica-Based Digital Audio Processors in Hearing Aids. MOCAST Jens Karrenbauer, Lukas Gerlach, Guillermo Payá-Vayá, Holger Blume
2020	J	`jnl`	Evolutionary Algorithms for Instruction Scheduling, Operation Merging, and Register Allocation in VLIW Compilers. J. Signal Process. Syst. Florian Giesemann, Lukas Gerlach, Guillermo Payá-Vayá
2020	—	`conf`	Issue-Slot Based Predication Encoding Technique for VLIW Processors. MOCAST Lukas Gerlach, Fabian Stuckmann, Holger Blume, Guillermo Payá-Vayá
2019	J	`jnl`	Comparing vertical and horizontal SIMD vector processor architectures for accelerated image feature extraction. J. Syst. Archit. Moritz Weißbrich, Alberto García Ortiz, Guillermo Payá-Vayá
2019	J	`jnl`	DNN-based performance measures for predicting error rates in automatic speech recognition and optimizing hearing aid parameters. Speech Commun. Angel Mario Castro Martinez, Lukas Gerlach, Guillermo Payá-Vayá, Hynek Hermansky, Jasper Ooster, Bernd T. Meyer
2019	J	`jnl`	Dynamic self-reconfiguration of a MIPS-based soft-core processor architecture. J. Parallel Distributed Comput. Stephan Nolting, Guillermo Payá-Vayá, Florian Giesemann, Holger Blume, Sebastian Niemann, Christian Müller-Schloer
2019	—	`conf`	Evaluation of Different Processor Architecture Organizations for On-site Electronics in Harsh Environments. SAMOS Sven Gesper, Moritz Weißbrich, Stephan Nolting, Tobias Stuckenberg, Pekka Jääskeläinen, Holger Blume, Guillermo Payá-Vayá
2019	J	`jnl`	FLINT+: A runtime-configurable emulation-based stochastic timing analysis framework. Integr. Moritz Weißbrich, Lukas Gerlach, Holger Blume, Ardalan Najafi, Alberto García Ortiz, Guillermo Payá-Vayá
2019	C	`conf`	KAVUAKA: A Low Power Application Specific Hearing Aid Processor. VLSI-SoC Lukas Gerlach, Guillermo Payá-Vayá, Holger Blume
2019	J	`jnl`	Online stereo camera calibration for automotive vision based on HW-accelerated A-KAZE-feature extraction. J. Syst. Archit. Nico Mentzer, Jannik Mahr, Guillermo Payá-Vayá, Holger Blume
2018	J	`jnl`	Coherent Design of Hybrid Approximate Adders: Unified Design Framework and Metrics. IEEE J. Emerg. Sel. Topics Circuits Syst. Ardalan Najafi, Moritz Weißbrich, Guillermo Payá-Vayá, Alberto García Ortiz
2017	—	`conf`	Analyzing the trade-off between power consumption and beamforming algorithm performance using a hearing aid ASIP. SAMOS Lukas Gerlach, Guillermo Payá-Vayá, Shuang Liu, Moritz Weißbrich, Holger Blume, Daniel Marquardt, Simon Doclo
2017	B	`conf`	Application-specific soft-core vector processor for advanced driver assistance systems. FPL Stephan Nolting, Florian Giesemann, Julian Hartig, Achim Schmider, Guillermo Payá-Vayá
2017	—	`conf`	Balanced application-specific processor system for efficient SIFT-feature detection. SAMOS Julian Hartig, Guillermo Payá-Vayá, Nico Mentzer, Holger Blume
2017	—	`conf`	FLINT+: A runtime-configurable emulation-based stochastic timing analysis framework. PATMOS Moritz Weißbrich, Guillermo Payá-Vayá, Lukas Gerlach, Holger Blume, Ardalan Najafi, Alberto García Ortiz
2017	J	`jnl`	Guest Editorial: Special Issue on the 2015 International Conference on Embedded Computer Systems - Architectures, Modeling and Simulation (SAMOS XV). Int. J. Parallel Program. Guillermo Payá-Vayá, Andreas Gerstlauer
2017	A	`conf`	Real-time implementation of a GMM-based binaural localization algorithm on a VLIW-SIMD processor. ICME Christopher Seifert, Joachim Thiemann, Lukas Gerlach, Tobias Volkmar, Guillermo Payá-Vayá, Holger Blume, Steven van de Par
2017	J	`jnl`	Small footprint synthesizable temperature sensor for FPGA devices. J. Syst. Archit. Guillermo Payá-Vayá, Christopher Bartels, Holger Blume
2017	—	`conf`	Tool-supported design space exploration of a processor system for SIFT-feature detection. ICCE-Berlin Julian Hartig, Guillermo Payá-Vayá, Henrik Heymann, Holger Blume
2017	B	`conf`	Two-LUT-based synthesizable temperature sensor for Virtex-6 FPGA devices. FPL Stephan Nolting, Lin Liu, Guillermo Payá-Vayá
2017	—	`conf`	Using a genetic algorithm approach to reduce register file pressure during instruction scheduling. SAMOS Florian Giesemann, Guillermo Payá-Vayá, Lukas Gerlach, Holger Blume, Fabian Pflug, Gabriele von Voigt
2016	J	`jnl`	Analyzing the Performance-Hardware Trade-off of an ASIP-based SIFT Feature Extraction. J. Signal Process. Syst. Nico Mentzer, Guillermo Payá-Vayá, Holger Blume
2016	—	`conf`	Customized high performance low power processor for binaural speaker localization. ICECS Nicolai Behmann, Christopher Seifert, Guillermo Payá-Vayá, Holger Blume, Pekka Jääskeläinen, Joonas Multanen, Heikki Kultala, Jarmo Takala, Joachim Thiemann, Steven van de Par
2016	—	`conf`	Dynamic Self-Reconfiguration of a MIPS-Based Soft-Processor Architecture. IPDPS Workshops Stephan Nolting, Guillermo Payá-Vayá, Florian Giesemann, Holger Blume, Sebastian Niemann, Christian Müller-Schloer
2016	—	`conf`	Efficient Emulation of Floating-Point Arithmetic on Fixed-Point SIMD Processors. SiPS Lukas Gerlach, Guillermo Payá-Vayá, Holger Blume
2016	—	`conf`	Performance monitoring for automatic speech recognition in noisy multi-channel environments. SLT Bernd T. Meyer, Sri Harish Reddy Mallidi, Angel Mario Castro Martinez, Guillermo Payá-Vayá, Hendrik Kayser, Hynek Hermansky
2015	—	`conf`	A Synthesizable Temperature Sensor on FPGA Using DSP-Slices for Reduced Calibration Overhead and Improved Stability. ARCS Christopher Bartels, Chao Zhang, Guillermo Payá-Vayá, Holger Blume
2015	—	`conf`	A mobile SoC-based platform for evaluating hearing aid algorithms and architectures. ICCE-Berlin Christopher Seifert, Guillermo Payá-Vayá, Holger Blume, Tobias Herzke, Volker Hohmann
2015	—	`conf`	An area efficient real- and complex-valued multiply-accumulate SIMD unit for digital signal processors. SiPS Lukas Gerlach, Guillermo Payá-Vayá, Holger Blume
2015	—	`conf`	Exploring Dynamic Reconfigurable CORDIC Co-Processors Tightly Coupled with a VLIW-SIMD Soft-Processor Architecture. ARC Stephan Nolting, Guillermo Payá-Vayá, Florian Giesemann, Holger Blume
2015	A	`conf`	FLINT: layout-oriented FPGA-based methodology for fault tolerant ASIC design. DATE Rochus Nowosielski, Lukas Gerlach, Stephan Bieband, Guillermo Payá-Vayá, Holger Blume
2015	—	`conf`	FNOCEE: A framework for NoC evaluation by FPGA-based emulation. SAMOS Daniel Pfefferkorn, Achim Schmider, Guillermo Payá-Vayá, Martin Neuenhahn, Holger Blume
2014	—	`conf`	A comprehensive ASIC/FPGA prototyping environment for exploring embedded processing systems for advanced driver assistance applications. ICSAMOS Florian Giesemann, Guillermo Payá-Vayá, Holger Blume, Matthias Limmer, Werner Ritter
2014	B	`conf`	ASEV - Automatic situation assessment for event-driven video analysis. AVSS Michele Fenzi, Jörn Ostermann, Nico Mentzer, Guillermo Payá-Vayá, Holger Blume, Tu Ngoc Nguyen, Thomas Risse
2014	—	`conf`	Customizing a VLIW-SIMD application-specific instruction-set processor for hearing aid devices. SiPS Julian Hartig, Lukas Gerlach, Guillermo Payá-Vayá, Holger Blume
2014	—	`conf`	Instruction-set extension for an ASIP-based SIFT feature extraction. ICSAMOS Nico Mentzer, Guillermo Payá-Vayá, Holger Blume, Nora von Egloffstein, Werner Ritter
2014	—	`conf`	Performance evaluation of the Intel Xeon Phi manycore architecture using parallel video-based driver assistance algorithms. ICSAMOS Oliver Jakob Arndt, Daniel Becker, Florian Giesemann, Guillermo Payá-Vayá, Christopher Bartels, Holger Blume
2010	J	`jnl`	A Multi-Shared Register File Structure for VLIW Processors. J. Signal Process. Syst. Guillermo Payá-Vayá, Javier Martín-Langerwerf, Peter Pirsch
2010	—	`conf`	A forwarding-sensitive instruction scheduling approach to reduce register file constraints in VLIW architectures. ASAP Guillermo Payá-Vayá, Javier Martín-Langerwerf, Holger Blume, Peter Pirsch
2009	—	`conf`	An Enhanced DMA Controller in SIMD Processors for Video Applications. ARCS Guillermo Payá-Vayá, Javier Martín-Langerwerf, Sören Moch, Peter Pirsch
2009	—	`conf`	Instruction merging to increase parallelism in VLIW architectures. SoC Guillermo Payá-Vayá, Javier Martín-Langerwerf, Florian Giesemann, Holger Blume, Peter Pirsch
2007	Misc	`conf`	ChipDesign: from theory to real world. WCAE Guillermo Payá-Vayá, Thomas Jambor, Konstantin Septinus, Sebastian Hesselbarth, Holger Flatt, Marc Freisfeld, Peter Pirsch
2007	—	`conf`	Design Space Exploration of Media Processors: A Generic VLIW Architecture and a Parameterized Scheduler. ARCS Guillermo Payá-Vayá, Javier Martín-Langerwerf, Piriya Taptimthong, Peter Pirsch
2007	—	`conf`	Design Space Exploration of Media Processors: A Parameterized Scheduler. ICSAMOS Guillermo Payá-Vayá, Javier Martín-Langerwerf, Piriya Taptimthong, Peter Pirsch
2007	C	`conf`	RAPANUI: A case study in Rapid Prototyping for Multiprocessor System-on-Chip. DSD Guillermo Payá-Vayá, Javier Martín-Langerwerf, Peter Pirsch