Guillaume Prenat

49 papers A* 1A 9B 2C 3Journal 16Unranked 18

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	Design of a Low-Power High-Density Analog in-Memory Computing Accelerator Using 18 Nm FD-SOI Phase-Change Memory. LATS V. Viollet, Guillaume Prenat, A. Al Muktash, C. Popon, Lorena Anghel, X. Lecoq
2025	—	`conf`	Temperature and Drift-Aware High-Level PCM-based Array Model for Reliable Hardware IMC Design. IRPS V. Viollet, E. Esmanhotto, M. Allegra, Matteo Baldo, Guillaume Prenat, Lorena Anghel, X. Lecoq
2024	A	`conf`	Enhancing Reliability of Neural Networks at the Edge: Inverted Normalization with Stochastic Affine Transformations. DATE Soyed Tuhin Ahmed, Kamal Danouchi, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
2024	J	`jnl`	Enhancing Reliability of Neural Networks at the Edge: Inverted Normalization with Stochastic Affine Transformations. CoRR Soyed Tuhin Ahmed, Kamal Danouchi, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
2024	A	`conf`	NeuSpin: Design of a Reliable Edge Neuromorphic System Based on Spintronics for Green AI. DATE Soyed Tuhin Ahmed, Kamal Danouchi, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
2024	J	`jnl`	NeuSpin: Design of a Reliable Edge Neuromorphic System Based on Spintronics for Green AI. CoRR Soyed Tuhin Ahmed, Kamal Danouchi, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
2024	B	`conf`	Testing Spintronics Implemented Monte Carlo Dropout-Based Bayesian Neural Networks. ETS Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
2024	J	`jnl`	Testing Spintronics Implemented Monte Carlo Dropout-Based Bayesian Neural Networks. CoRR Soyed Tuhin Ahmed, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
2023	J	`jnl`	A tunable and versatile 28nm FD-SOI crossbar output circuit for low power analog SNN inference with eNVM synapses. CoRR Joao Henrique Quintino Palhares, Yann Beilliard, Jury Sandrini, Franck Arnaud, Kevin Garello, Guillaume Prenat, Lorena Anghel, Fabien Alibart, Dominique Drouin, Philippe Galy
2023	—	`conf`	Robustness and Power Efficiency in Spin-Orbit Torque-Based Probabilistic Logic Circuits. ISVLSI Kamal Danouchi, Guillaume Prenat, Philippe Talatchian, Louis Hutin, Lorena Anghel
2023	A	`conf`	Scalable Spintronics-based Bayesian Neural Network for Uncertainty Estimation. DATE Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
2023	J	`jnl`	Scale-Dropout: Estimating Uncertainty in Deep Neural Networks Using Stochastic Scale. CoRR Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
2023	J	`jnl`	Spatial-SpinDrop: Spatial Dropout-based Binary Bayesian Neural Network with Spintronics Implementation. CoRR Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
2023	J	`jnl`	SpinBayes: Algorithm-Hardware Co-Design for Uncertainty Estimation Using Bayesian In-Memory Approximation on Spintronic-Based Architectures. ACM Trans. Embed. Comput. Syst. Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
2023	J	`jnl`	SpinDrop: Dropout-Based Bayesian Binary Neural Networks With Spintronic Implementation. IEEE J. Emerg. Sel. Topics Circuits Syst. Soyed Tuhin Ahmed, Kamal Danouchi, Christopher Münch, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
2023	J	`jnl`	Spintronic Memristor-Based Binarized Ensemble Convolutional Neural Network Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ghislain Takam Tchendjou, Kamal Danouchi, Guillaume Prenat, Lorena Anghel
2022	J	`jnl`	A Fast, Energy Efficient and Tunable Magnetic Tunnel Junction Based Bitstream Generator for Stochastic Computing. IEEE Trans. Circuits Syst. I Regul. Pap. Etienne Becle, Guillaume Prenat, Philippe Talatchian, Lorena Anghel, Ioan Lucian Prejbeanu
2022	—	`conf`	Binary Bayesian Neural Networks for Efficient Uncertainty Estimation Leveraging Inherent Stochasticity of Spintronic Devices. NANOARCH Soyed Tuhin Ahmed, Kamal Danouchi, Christopher Münch, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori
2022	C	`conf`	MemCork: Exploration of Hybrid Memory Architectures for Intermittent Computing at the Edge. VLSI-SoC Theo Soriano, David Novo, Guillaume Prenat, Gregory di Pendina, Pascal Benoit
2022	—	`conf`	Spin Orbit Torque-based Crossbar Array for Error Resilient Binary Convolutional Neural Network. LATS Kamal Danouchi, Guillaume Prenat, Lorena Anghel
2021	—	`conf`	Fast Behavioral VerilogA Compact Model for Stochastic MTJ. ESSDERC Etienne Becle, Philippe Talatchian, Guillaume Prenat, Lorena Anghel, Ioan Lucian Prejbeanu
2020	A	`conf`	A Universal Spintronic Technology based on Multifunctional Standardized Stack. DATE Mehdi Baradaran Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, Lionel Torres, Sophiane Senni, Guillaume Patrigeon, Pascal Benoit, Gregory di Pendina, Guillaume Prenat
2019	J	`jnl`	Design and Evaluation of a 28-nm FD-SOI STT-MRAM for Ultra-Low Power Microcontrollers. IEEE Access Guillaume Patrigeon, Pascal Benoit, Lionel Torres, Sophiane Senni, Guillaume Prenat, Gregory di Pendina
2018	C	`conf`	From Spintronic Devices to Hybrid CMOS/Magnetic System On Chip. VLSI-SoC Sophiane Senni, Frederic Ouattara, Jad Mohdad, Kaan Sevin, Guillaume Patrigeon, Pascal Benoit, Pascal Nouet, Lionel Torres, François Duhem, Gregory di Pendina, Guillaume Prenat
2018	—	`conf`	MRAM: from STT to SOT, for security and memory. DCIS Mounia Kharbouche-Harrari, Rana Alhalabi, Jérémy Postel-Pellerin, Romain Wacquez, Driss Aboulkassimi, Etienne Nowak, Ioan Lucian Prejbeanu, Guillaume Prenat, Gregory di Pendina
2018	C	`conf`	Resistive and Spintronic RAMs: Device, Simulation, and Applications. IOLTS Elena-Ioana Vatajelu, Lorena Anghel, Jean-Michel Portal, Marc Bocquet, Guillaume Prenat
2018	A	`conf`	Using multifunctional standardized stack as universal spintronic technology for IoT. DATE Mehdi Baradaran Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, Sophiane Senni, Jad Mohdad, Frédérick Mailly, Lionel Torres, Pascal Benoit, Abdoulaye Gamatié, Pascal Nouet, Frederic Ouattara, Gilles Sassatelli, Kotb Jabeur, Pierre Vanhauwaert, A. Atitoaie, I. Firastrau, Gregory di Pendina, Guillaume Prenat
2017	—	`conf`	GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack. ISVLSI Mehdi Baradaran Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, Sophiane Senni, Jad Mohdad, Frédérick Mailly, Lionel Torres, Pascal Benoit, Pascal Nouet, Rui Ma, Martin Kreißig, Frank Ellinger, Kotb Jabeur, Pierre Vanhauwaert, Gregory di Pendina, Guillaume Prenat
2016	—	`conf`	Multi-context non-volatile content addressable memory using magnetic tunnel junctions. NANOARCH Erya Deng, Lorena Anghel, Guillaume Prenat, Weisheng Zhao
2016	J	`jnl`	Reducing System Power Consumption Using Check-Pointing on Nonvolatile Embedded Magnetic Random Access Memories. ACM J. Emerg. Technol. Comput. Syst. Christophe Layer, Laurent Becker, Kotb Jabeur, Sylvain Claireux, Bernard Dieny, Guillaume Prenat, Gregory di Pendina, Stephane Gros, Pierre Paoli, Virgile Javerliac, Fabrice Bernard-Granger, Loïc Decloedt
2016	J	`jnl`	Ultra-Fast and High-Reliability SOT-MRAM: From Cache Replacement to Normally-Off Computing. IEEE Trans. Multi Scale Comput. Syst. Guillaume Prenat, Kotb Jabeur, Pierre Vanhauwaert, Gregory di Pendina, Fabian Oboril, Rajendra Bishnoi, Mojtaba Ebrahimi, Nathalie Lamard, Olivier Boulle, Kevin Garello, Juergen Langer, Berthold Ocker, Marie Claire Cyrille, Pietro Gambardella, Mehdi Baradaran Tahoori, Gilles Gaudin
2015	—	`conf`	Robust magnetic full-adder with voltage sensing 2T/2MTJ cell. NANOARCH Erya Deng, You Wang, Zhaohao Wang, Jacques-Olivier Klein, Bernard Dieny, Guillaume Prenat, Weisheng Zhao
2015	J	`jnl`	Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction. IEEE Trans. Circuits Syst. I Regul. Pap. Erya Deng, Yue Zhang, Wang Kang, Bernard Dieny, Jacques-Olivier Klein, Guillaume Prenat, Weisheng Zhao
2014	—	`conf`	Hybrid CMOS/magnetic Process Design Kit and SOT-based non-volatile standard cell architectures. ASP-DAC Gregory di Pendina, Kotb Jabeur, Guillaume Prenat
2014	—	`conf`	InMRAM: Introductory course on Magnetic Random Access Memories for microelectronics students and engineers. EWME Gregory di Pendina, Guillaume Prenat, Bernard Dieny
2014	A	`conf`	Magnetic memories: From DRAM replacement to ultra low power logic chips. DATE Guillaume Prenat, Gregory di Pendina, Christophe Layer, Olivier Goncalves, K. Jaber, Bernard Dieny, Ricardo C. Sousa, Ioan Lucian Prejbeanu, Jean-Pierre Nozieres
2013	—	`conf`	Emerging hybrid logic circuits based on non-volatile magnetic memories. NEWCAS Weisheng Zhao, Guillaume Prenat, Jacques-Olivier Klein, Bernard Dieny, Claude Chappert, Dafine Ravelosona
2013	A*	`conf`	Non-volatile FPGAs based on spintronic devices. DAC Olivier Goncalves, Guillaume Prenat, Gregory di Pendina, Bernard Dieny
2012	B	`conf`	Coupling-based resistive-open defects in TAS-MRAM architectures. ETS Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay
2012	—	`conf`	Impact of Resistive-Bridge Defects in TAS-MRAM Architectures. Asian Test Symposium Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay
2012	A	`conf`	Impact of resistive-open defects on the heat current of TAS-MRAM architectures. DATE Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay
2011	A	`conf`	Hybrid CMOS/Magnetic Process Design Kit and application to the design of high-performances non-volatile logic circuits. ICCAD Guillaume Prenat, Bernard Dieny, Jean-Pierre Nozieres, Gregory di Pendina, Kholdoun Torki
2011	—	`conf`	Ultra Compact Non-volatile Flip-Flop for Low Power Digital Circuits Based on Hybrid CMOS/Magnetic Technology. PATMOS Gregory di Pendina, Kholdoun Torki, Guillaume Prenat, Yoann Guillemenet, Lionel Torres
2009	J	`jnl`	TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA. ACM Trans. Reconfigurable Technol. Syst. Weisheng Zhao, Eric Belhaire, Claude Chappert, Bernard Dieny, Guillaume Prenat
2007	—	`conf`	CMOS/Magnetic Hybrid Architectures. ICECS Guillaume Prenat, Mourad El Baraji, Wei Guo, Ricardo Sousa, Liliana Buda-Prejbeanu, Bernard Dieny, Virgile Javerliac, Jean-Pierre Nozieres, Weisheng Zhao, Eric Belhaire
2007	—	`conf`	TAS-MRAM based Non-volatile FPGA logic circuit. FPT Weisheng Zhao, Eric Belhaire, Bernard Dieny, Guillaume Prenat, Claude Chappert
2005	—	`conf`	A built-in I ESSCIRC Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Th. Haniotakis, Guillaume Prenat, Salvador Mir
2005	J	`jnl`	A low-cost digital frequency testing approach for mixed-signal devices using SigmaDelta modulation. Microelectron. J. Guillaume Prenat, Salvador Mir, Diego Vázquez, Luís Rolíndez
2004	A	`conf`	A 0.18 µm CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns. DATE Luís Rolíndez, Salvador Mir, Guillaume Prenat, Ahcène Bounceur