Guilherme Flach

21 papers C 2Journal 2Unranked 17
YearRankTypeTitle / Venue / Authors
2017 — conf
Rsyn: An Extensible Physical Synthesis Framework.
ISPD
Guilherme Flach, Mateus Fogaça, Jucemar Monteiro, Marcelo O. Johann, Ricardo Augusto da Luz Reis
2016 — conf
Drive Strength Aware Cell Movement Techniques for Timing Driven Placement.
ISPD
Guilherme Flach, Mateus Fogaça, Jucemar Monteiro, Marcelo O. Johann, Ricardo Augusto da Luz Reis
2016 — conf
Improving placement algorithms by using visualization tools.
NEWCAS
Mateus Fogaça, Guilherme Flach, Marcelo O. Johann, Ricardo Augusto da Luz Reis
2016 — conf
Leakage current analysis in static CMOS logic gates for a transistor network design approach.
PATMOS
Jorge L. Tonfat, Guilherme Flach, Ricardo Reis
2016 — conf
Quadratic timing objectives for incremental timing-driven placement optimization.
ICECS
Mateus Fogaça, Guilherme Flach, Jucemar Monteiro, Marcelo O. Johann, Ricardo Reis
2016 — conf
Routing-Aware Incremental Timing-Driven Placement.
ISVLSI
Jucemar Monteiro, Nima Karimpour Darav, Guilherme Flach, Mateus Fogaça, Ricardo Augusto da Luz Reis, Andrew A. Kennings, Marcelo O. Johann, Laleh Behjat
2015 C conf
An Incremental Timing-Driven flow using quadratic formulation for detailed placement.
VLSI-SoC
Guilherme Flach, Jucemar Monteiro, Mateus Fogaça, Julia Casarin Puget, Paulo F. Butzen, Marcelo O. Johann, Ricardo Augusto da Luz Reis
2015 — conf
An analytical timing-driven algorithm for detailed placement.
LASCAS
Jucemar Monteiro, Guilherme Flach, Marcelo O. Johann, José Luís Almada Güntzel
2015 — conf
Jezz: An Effective Legalization Algorithm for Minimum Displacement.
SBCCI
Julia Casarin Puget, Guilherme Flach, Marcelo O. Johann, Ricardo Augusto da Luz Reis
2014 — conf
A tool to simulate optical lithography in nanoCMOs.
I2MTC
Tania Mara Ferla, Guilherme Flach, Ricardo Reis
2014 J jnl
Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Guilherme Flach, Tiago Reimann, Gracieli Posser, Marcelo O. Johann, Ricardo Reis
2013 C conf
Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing.
ISCAS
Tiago Reimann, Gracieli Posser, Guilherme Flach, Marcelo O. Johann, Ricardo Reis
2013 — conf
Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities.
ISVLSI
Guilherme Flach, Tiago Reimann, Gracieli Posser, Marcelo O. Johann, Ricardo Reis
2012 J jnl
High-performance clock mesh optimization.
ACM Trans. Design Autom. Electr. Syst.
Matthew R. Guthaus, Xuchu Hu, Gustavo Wilke, Guilherme Flach, Ricardo Reis
2012 — conf
Transistor sizing and gate sizing using geometric programming considering delay minimization.
NEWCAS
Gracieli Posser, Guilherme Flach, Gustavo Wilke, Ricardo Reis
2011 — conf
Gate Sizing Minimizing Delay and Area.
ISVLSI
Gracieli Posser, Guilherme Flach, Gustavo Wilke, Ricardo Reis
2011 — conf
Quadratic placement with single-iteration linear system solver.
SBCCI
Guilherme Flach, Marcelo O. Johann, Ricardo Reis
2010 — conf
A Mesh-Buffer Displacement Optimization Strategy.
ISVLSI
Guilherme Flach, Gustavo Wilke, Marcelo O. Johann, Ricardo Reis
2007 — conf
3D-Vias Aware Quadratic Placement for 3D VLSI Circuits.
ISVLSI
Renato Fernandes Hentschke, Guilherme Flach, Felipe Pinto, Ricardo Reis
2007 — conf
Cell placement on graphics processing units.
SBCCI
Guilherme Flach, Marcelo O. Johann, Renato Fernandes Hentschke, Ricardo Reis
2006 — conf
Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing.
SBCCI
Renato Fernandes Hentschke, Guilherme Flach, Felipe Pinto, Ricardo Reis