Guido Masera - RankMe

208 papers A* 2A 12B 12C 11Misc 4Journal 102Unranked 65

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	A Deep Dive into Integration Methodologies in RISC-V. CF (Companion) Valeria Piscopo, Alessandra Dolmeta, Mattia Mirigaldi, Maurizio Martina, Guido Masera
2025	A*	`conf`	ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions. DAC Vincenzo Petrolo, Flavia Guella, Michele Caon, Pasquale Davide Schiavone, Guido Masera, Maurizio Martina
2025	J	`jnl`	ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions. CoRR Vincenzo Petrolo, Flavia Guella, Michele Caon, Pasquale Davide Schiavone, Guido Masera, Maurizio Martina
2025	—	`conf`	CHIMERA: Cryptographic Hardware for Integrated Multipurpose Engine on RISC-V with ASCON. ISVLSI Alessandra Dolmeta, Valeria Piscopo, Maurizio Martina, Guido Masera
2025	J	`jnl`	HORCRUX - A Lightweight PQC-RISC-V eXtension Architecture. IACR Cryptol. ePrint Arch. Alessandra Dolmeta, Valeria Piscopo, Guido Masera, Maurizio Martina, Michael Hutter
2025	—	`conf`	Just TestIt! An SBST Approach To Automate System-Integration Testing. CF (Companion) Tommaso Terzano, Luigi Giuffrida, Juan Sapriza, Pasquale Davide Schiavone, Guido Masera, David Atienza, Luciano Lavagno, Maurizio Martina
2025	J	`jnl`	Just TestIt! An SBST Approach To Automate System-Integration Testing. CoRR Tommaso Terzano, Luigi Giuffrida, Juan Sapriza, Pasquale Davide Schiavone, Guido Masera, David Atienza, Luciano Lavagno, Maurizio Martina
2025	A	`conf`	Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF). ITC Behnam Farnaghinejad, Davide Bellizia, Alessandra Dolmeta, Guido Masera, Antonio Porsia, Annachiara Ruospo, Stefano Di Carlo, Alessandro Savino, Ernesto Sánchez
2025	C	`conf`	RISC-V Based Keccak Co-Processor for NIST Post-Quantum Cryptography Standards. ISCAS Alessandra Dolmeta, Valeria Piscopo, Mattia Mirigaldi, Maurizio Martina, Guido Masera
2025	C	`conf`	Scalability analysis of multi-bank near-memory computing in low-power SoCs. VLSI-SoC Luigi Giuffrida, Pasquale Davide Schiavone, Michele Caon, Guido Masera, Maurizio Martina, David Atienza
2025	J	`jnl`	Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes. IEEE Trans. Emerg. Top. Comput. Michele Caon, Clément Choné, Pasquale Davide Schiavone, Alexandre Levisse, Guido Masera, Maurizio Martina, David Atienza
2025	—	`conf`	Stop Wasting your Cache! Bringing Machine Learning into Cache Computing. CF (Companion) Vincenzo Petrolo, Flavia Guella, Michele Caon, Guido Masera, Maurizio Martina
2025	A	`conf`	TYRCA: A RISC-V Tightly-Coupled Accelerator for Code-Based Cryptography. DATE Alessandra Dolmeta, Stefano Di Matteo, Emanuele Valea, Mikael Carmona, Antoine Loiseau, Maurizio Martina, Guido Masera
2025	B	`conf`	TinyCL: An Efficient Hardware Architecture for Continual Learning on Autonomous Systems. IJCNN Eugenio Ressa, Alberto Marchisio, Maurizio Martina, Guido Masera, Muhammad Shafique
2024	J	`jnl`	ATHOS: A Hybrid Accelerator for PQC CRYSTALS-Algorithms Exploiting New CV-X-IF Interface. IEEE Access Alessandra Dolmeta, Maurizio Martina, Guido Masera
2024	—	`conf`	Exploring the New CV-X-IF Interface to Customize RISC-V Instruction Sets: A Case of Study in Cryptography. ApplePies Alessandra Dolmeta, Maurizio Martina, Guido Masera
2024	—	`conf`	Implementation and integration of NTT/INTT accelerator on RISC-V for CRYSTALS-Kyber. CF (Companion) Alessandra Dolmeta, Emanuele Valpreda, Maurizio Martina, Guido Masera
2024	J	`jnl`	MARLIN: A Co-Design Methodology for Approximate ReconfigurabLe Inference of Neural Networks at the Edge. IEEE Trans. Circuits Syst. I Regul. Pap. Flavia Guella, Emanuele Valpreda, Michele Caon, Guido Masera, Maurizio Martina
2024	—	`conf`	Performance Comparison: Software vs. Hardware Implementation of Novel S-Box Designed to Resist Power Analysis Attack. ApplePies Mattia Mirigaldi, Maurizio Martina, Guido Masera
2024	J	`jnl`	Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes. CoRR Michele Caon, Clément Choné, Pasquale Davide Schiavone, Alexandre Levisse, Guido Masera, Maurizio Martina, David Atienza
2024	—	`conf`	Seeing Beyond the Order: a LEN5 to Sharpen Edge Microprocessors with Dynamic Scheduling. CF (Companion) Michele Caon, Vincenzo Petrolo, Mattia Mirigaldi, Flavia Guella, Guido Masera, Maurizio Martina
2024	J	`jnl`	TinyCL: An Efficient Hardware Architecture for Continual Learning on Autonomous Systems. CoRR Eugenio Ressa, Alberto Marchisio, Maurizio Martina, Guido Masera, Muhammad Shafique
2023	J	`jnl`	A Flexible NTT-Based Multiplier for Post-Quantum Cryptography. IEEE Access Kristjane Koleci, Paolo Mazzetti, Maurizio Martina, Guido Masera
2023	J	`jnl`	Architectural Comparison Model for Area-Efficient PMAP Turbo-Decoders. IEEE Trans. Circuits Syst. II Express Briefs Simone Favero, Maurizio Martina, Guido Masera
2023	J	`jnl`	Comparative Study of Keccak SHA-3 Implementations. Cryptogr. Alessandra Dolmeta, Maurizio Martina, Guido Masera
2023	J	`jnl`	Custom Memory Design for Logic-in-Memory: Drawbacks and Improvements over Conventional Memories. CoRR Fabrizio Ottati, Giovanna Turvani, Marco Vacca, Guido Masera
2023	—	`conf`	ERODE: Error Resilient Object DetEction by Recovering Bounding Box and Class Information. PRIME Emanuele Valpreda, Giuseppe Palumbo, Michele Caon, Guido Masera, Maurizio Martina
2023	—	`conf`	Hardware architecture for CRYSTALS-Kyber post-quantum cryptographic SHA-3 primitives. PRIME Alessandra Dolmeta, Maurizio Martina, Guido Masera
2023	—	`conf`	Implementation and integration of Keccak accelerator on RISC-V for CRYSTALS-Kyber. CF Alessandra Dolmeta, Mattia Mirigaldi, Maurizio Martina, Guido Masera
2023	—	`conf`	LOKI Low-Latency Open-Source Kyber-Accelerator IPs. ApplePies Alessandra Dolmeta, Mattia Mirigaldi, Maurizio Martina, Guido Masera
2023	—	`conf`	RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project. SAMOS William Fornaciari, Federico Reghenzani, Giovanni Agosta, Davide Zoni, Andrea Galimberti, Francesco Conti, Yvan Tortorella, Emanuele Parisi, Francesco Barchi, Andrea Bartolini, Andrea Acquaviva, Daniele Gregori, Salvatore Cognetta, Carlo Ciancarelli, Antonio Leboffe, Paolo Serri, Alessio Burrello, Daniele Jahier Pagliari, Gianvito Urgese, Maurizio Martina, Guido Masera, Rosario Di Carlo, Antonio Sciarappa
2023	B	`conf`	SwiftTron: An Efficient Hardware Accelerator for Quantized Transformers. IJCNN Alberto Marchisio, Davide Dura, Maurizio Capra, Maurizio Martina, Guido Masera, Muhammad Shafique
2023	J	`jnl`	SwiftTron: An Efficient Hardware Accelerator for Quantized Transformers. CoRR Alberto Marchisio, Davide Dura, Maurizio Capra, Maurizio Martina, Guido Masera, Muhammad Shafique
2023	—	`conf`	TEMET: Truncated REconfigurable Multiplier with Error Tuning. ApplePies Flavia Guella, Emanuele Valpreda, Michele Caon, Guido Masera, Maurizio Martina
2022	—	`conf`	A Side Channel Attack Methodology Applied to Code-Based Post Quantum Cryptography. ApplePies Kristjane Koleci, Lorenzo Cecchetti, Guido Masera, Maurizio Martina, Massimo Ruo Roch
2022	B	`conf`	CoNLoCNN: Exploiting Correlation and Non-Uniform Quantization for Energy-Efficient Low-precision Deep Convolutional Neural Networks. IJCNN Muhammad Abdullah Hanif, Giuseppe Maria Sarda, Alberto Marchisio, Guido Masera, Maurizio Martina, Muhammad Shafique
2022	J	`jnl`	CoNLoCNN: Exploiting Correlation and Non-Uniform Quantization for Energy-Efficient Low-precision Deep Convolutional Neural Networks. CoRR Muhammad Abdullah Hanif, Giuseppe Maria Sarda, Alberto Marchisio, Guido Masera, Maurizio Martina, Muhammad Shafique
2022	A	`conf`	Enabling Capsule Networks at the Edge through Approximate Softmax and Squash Operations. ISLPED Alberto Marchisio, Beatrice Bussolino, Edoardo Salvati, Maurizio Martina, Guido Masera, Muhammad Shafique
2022	J	`jnl`	Enabling Capsule Networks at the Edge through Approximate Softmax and Squash Operations. CoRR Alberto Marchisio, Beatrice Bussolino, Edoardo Salvati, Maurizio Martina, Guido Masera, Muhammad Shafique
2022	A	`conf`	LaneSNNs: Spiking Neural Networks for Lane Detection on the Loihi Neuromorphic Processor. IROS Alberto Viale, Alberto Marchisio, Maurizio Martina, Guido Masera, Muhammad Shafique
2022	J	`jnl`	LaneSNNs: Spiking Neural Networks for Lane Detection on the Loihi Neuromorphic Processor. CoRR Alberto Viale, Alberto Marchisio, Maurizio Martina, Guido Masera, Muhammad Shafique
2022	B	`conf`	NLCMAP: A Framework for the Efficient Mapping of Non-Linear Convolutional Neural Networks on FPGA Accelerators. ICIP Giuseppe Aiello, Beatrice Bussolino, Emanuele Valpreda, Massimo Ruo Roch, Guido Masera, Maurizio Martina, Stefano Marsi
2021	B	`conf`	CarSNN: An Efficient Spiking Neural Network for Event-Based Autonomous Cars on the Loihi Neuromorphic Research Processor. IJCNN Alberto Viale, Alberto Marchisio, Maurizio Martina, Guido Masera, Muhammad Shafique
2021	J	`jnl`	CarSNN: An Efficient Spiking Neural Network for Event-Based Autonomous Cars on the Loihi Neuromorphic Research Processor. CoRR Alberto Viale, Alberto Marchisio, Maurizio Martina, Guido Masera, Muhammad Shafique
2021	B	`conf`	DVS-Attacks: Adversarial Attacks on Dynamic Vision Sensors for Spiking Neural Networks. IJCNN Alberto Marchisio, Giacomo Pira, Maurizio Martina, Guido Masera, Muhammad Shafique
2021	J	`jnl`	DVS-Attacks: Adversarial Attacks on Dynamic Vision Sensors for Spiking Neural Networks. CoRR Alberto Marchisio, Giacomo Pira, Maurizio Martina, Guido Masera, Muhammad Shafique
2021	J	`jnl`	Efficient Hardware Implementation of the LEDAcrypt Decoder. IEEE Access Kristjane Koleci, Paolo Santini, Marco Baldi, Franco Chiaraluce, Maurizio Martina, Guido Masera
2021	A	`conf`	R-SNN: An Analysis and Design Methodology for Robustifying Spiking Neural Networks against Adversarial Attacks through Noise Filters for Dynamic Vision Sensors. IROS Alberto Marchisio, Giacomo Pira, Maurizio Martina, Guido Masera, Muhammad Shafique
2021	J	`jnl`	R-SNN: An Analysis and Design Methodology for Robustifying Spiking Neural Networks against Adversarial Attacks through Noise Filters for Dynamic Vision Sensors. CoRR Alberto Marchisio, Giacomo Pira, Maurizio Martina, Guido Masera, Muhammad Shafique
2021	J	`jnl`	Real-time implementation of fast discriminative scale space tracking algorithm. J. Real Time Image Process. Walid Walid, Muhammad Awais, Ashfaq Ahmed, Guido Masera, Maurizio Martina
2020	Misc	`conf`	A Fast Design Space Exploration Framework for the Deep Learning Accelerators: Work-in-Progress. CODES+ISSS Alessio Colucci, Alberto Marchisio, Beatrice Bussolino, Vojtech Mrazek, Maurizio Martina, Guido Masera, Muhammad Shafique
2020	—	`conf`	A Hardware Implementation for Code-based Post-quantum Asymmetric Cryptography. ITASEC Kristjane Koleci, Marco Baldi, Maurizio Martina, Guido Masera
2020	J	`jnl`	An Area-Efficient Variable-Size Fixed-Point DCT Architecture for HEVC Encoding. IEEE Trans. Circuits Syst. Video Technol. Maurizio Masera, Guido Masera, Maurizio Martina
2020	J	`jnl`	An Updated Survey of Efficient Hardware Architectures for Accelerating Deep Convolutional Neural Networks. Future Internet Maurizio Capra, Beatrice Bussolino, Alberto Marchisio, Muhammad Shafique, Guido Masera, Maurizio Martina
2020	B	`conf`	FasTrCaps: An Integrated Framework for Fast yet Accurate Training of Capsule Networks. IJCNN Alberto Marchisio, Beatrice Bussolino, Alessio Colucci, Muhammad Abdullah Hanif, Maurizio Martina, Guido Masera, Muhammad Shafique
2020	J	`jnl`	Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead. IEEE Access Maurizio Capra, Beatrice Bussolino, Alberto Marchisio, Guido Masera, Maurizio Martina, Muhammad Shafique
2020	J	`jnl`	Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead. CoRR Maurizio Capra, Beatrice Bussolino, Alberto Marchisio, Guido Masera, Maurizio Martina, Muhammad Shafique
2020	J	`jnl`	Low-Complexity Reconfigurable DCT-V Architecture. IEEE Trans. Circuits Syst. Jurgen Kello, Massimo Ruo Roch, Guido Masera, Maurizio Martina
2020	A*	`conf`	Q-CapsNets: A Specialized Framework for Quantizing Capsule Networks. DAC Alberto Marchisio, Beatrice Bussolino, Alessio Colucci, Maurizio Martina, Guido Masera, Muhammad Shafique
2020	J	`jnl`	Q-CapsNets: A Specialized Framework for Quantizing Capsule Networks. CoRR Alberto Marchisio, Beatrice Bussolino, Alessio Colucci, Maurizio Martina, Guido Masera, Muhammad Shafique
2020	J	`jnl`	Steerable-Discrete-Cosine-Transform (SDCT): Hardware Implementation and Performance Analysis. Sensors Riccardo Peloso, Maurizio Capra, Luigi Sole, Massimo Ruo Roch, Guido Masera, Maurizio Martina
2019	J	`jnl`	Edge Computing: A Survey On the Hardware Requirements in the Internet of Things World. Future Internet Maurizio Capra, Riccardo Peloso, Guido Masera, Massimo Ruo Roch, Maurizio Martina
2019	J	`jnl`	LDPC check node implementation using reversible logic. IET Circuits Devices Syst. Muhammad Awais, Anas Razzaq, Ashfaq Ahmed, Guido Masera
2019	J	`jnl`	On the Effect of Approximate-Computing in Motion Estimation. J. Low Power Electron. Alberto Paltrinieri, Riccardo Peloso, Guido Masera, Muhammad Shafique, Maurizio Martina
2019	—	`conf`	VLSI Architectures for the Steerable-Discrete-Cosine-Transform (SDCT). ApplePies Luigi Sole, Riccardo Peloso, Maurizio Capra, Massimo Ruo Roch, Guido Masera, Maurizio Martina
2019	J	`jnl`	X-TrainCaps: Accelerated Training of Capsule Nets through Lightweight Software Optimizations. CoRR Alberto Marchisio, Beatrice Bussolino, Alessio Colucci, Muhammad Abdullah Hanif, Maurizio Martina, Guido Masera, Muhammad Shafique
2018	J	`jnl`	A Multi-Kernel Multi-Code Polar Decoder Architecture. CoRR Gabriele Coppolino, Carlo Condo, Guido Masera, Warren J. Gross
2018	J	`jnl`	A Multi-Kernel Multi-Code Polar Decoder Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. Gabriele Coppolino, Carlo Condo, Guido Masera, Warren J. Gross
2018	—	`conf`	An Optimized Partial-Distortion-Elimination Based Sum-of-Absolute-Differences Architecture for High-Efficiency-Video-Coding. ApplePies Paolo Selvo, Maurizio Masera, Riccardo Peloso, Guido Masera, Muhammad Shafique, Maurizio Martina
2018	—	`conf`	Approximate-Computing Architectures for Motion Estimation in HEVC. NGCAS Alberto Paltrinieri, Riccardo Peloso, Guido Masera, Muhammad Shafique, Maurizio Martina
2018	—	`conf`	Efficient Operation Scheduling in Successive-Cancellation-based polar decoders. SiPS Gabriele Coppolino, Carlo Condo, Guido Masera, Warren J. Gross
2017	—	`conf`	A low power architecture for AER event-processing microcontroller. BioCAS Simone Aiassa, Paolo Motto Ros, Guido Masera, Maurizio Martina
2017	J	`jnl`	Adaptive Approximated DCT Architectures for HEVC. IEEE Trans. Circuits Syst. Video Technol. Maurizio Masera, Maurizio Martina, Guido Masera
2017	J	`jnl`	Analysis of HEVC transform throughput requirements for hardware implementations. Signal Process. Image Commun. Maurizio Masera, Lorenzo Re Fiorentin, Enrico Masala, Guido Masera, Maurizio Martina
2017	—	`conf`	Approximate Arai DCT Architecture for HEVC. NGCAS Giovanni Renda, Maurizio Masera, Maurizio Martina, Guido Masera
2017	—	`conf`	Low-Power Hardware Accelerator for Sparse Matrix Convolution in Deep Neural Network. IIH-MSP (1) Erik Anzalone, Maurizio Capra, Riccardo Peloso, Maurizio Martina, Guido Masera
2017	—	`conf`	Odd type DCT/DST for video coding: Relationships and low-complexity implementations. SiPS Maurizio Masera, Maurizio Martina, Guido Masera
2016	J	`jnl`	Automotive Power-Line Communication Channels: Mathematical Characterization and Hardware Emulator. IEEE Trans. Ind. Electron. Lorenzo Guerrieri, Guido Masera, Igor S. Stievano, Paola Bisaglia, Williams Richard Garcia Valverde, Mara Concolato
2016	—	`conf`	Comparison between HEVC and Thor based on objective and subjective assessments. IWSSIP Lorenzo Re Fiorentin, Maurizio Masera, Sabino Mantovano, Paola Sunna, Guido Masera, Maurizio Martina
2016	J	`jnl`	FPGA Accelerator of Algebraic Quasi Cyclic LDPC Codes for nand Flash Memories. IEEE Des. Test Syed Azhar Ali Zaidi, Abuduwaili Tuoheti, Maurizio Martina, Guido Masera
2016	—	`conf`	High Level Synthesis based FPGA Implementation of H.264/AVC Sub-Pixel Luma Interpolation Filters. EMS Waqar Ahmad, Javed Iqbal, Maurizio Martina, Guido Masera
2015	A	`conf`	An all-digital spike-based ultra-low-power IR-UWB dynamic average threshold crossing scheme for muscle force wireless transmission. DATE Masoud Shahshahani Amirhossein, Paolo Motto Ros, Alberto Bonanno, Marco Crepaldi, Maurizio Martina, Danilo Demarchi, Guido Masera
2015	J	`jnl`	Comments on "Bitwise Log-Likelihood Ratios for Quadrature Amplitude Modulations". IEEE Commun. Lett. Stylianos Papaharalabos, P. Takis Mathiopoulos, Maurizio Martina, Guido Masera
2015	—	`conf`	Complexity and implementation analysis of synthesized view distortion estimation architecture in 3D High Efficiency Video Coding. IC3D Waqar Ahmad, Maurizio Martina, Guido Masera
2015	J	`jnl`	Exploiting generalized de-Bruijn/Kautz topologies for flexible iterative channel code decoder architectures. Integr. Carlo Condo, Maurizio Martina, Massimo Ruo Roch, Guido Masera
2015	—	`conf`	Optimizing the transform complexity-quality tradeoff for hardware-accelerated HEVC video coding. DASIP Maurizio Masera, Lorenzo Re Fiorentin, Maurizio Martina, Guido Masera, Enrico Masala
2015	J	`jnl`	Parallel H.264/AVC Fast Rate-Distortion Optimized Motion Estimation by Using a Graphics Processing Unit and Dedicated Hardware. IEEE Trans. Circuits Syst. Video Technol. Muhammad Usman Shahid, Ashfaq Ahmed, Maurizio Martina, Guido Masera, Enrico Magli
2015	J	`jnl`	Reducing the Dissipated Energy in Multi-standard Turbo and LDPC Decoders. Circuits Syst. Signal Process. Carlo Condo, Amer Baghdadi, Guido Masera
2015	J	`jnl`	Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT. IEEE Trans. Circuits Syst. I Regul. Pap. Maurizio Martina, Guido Masera, Massimo Ruo Roch, Gianluca Piccinini
2015	J	`jnl`	Unequal Error Protection of Memories in LDPC Decoders. IEEE Trans. Computers Carlo Condo, Guido Masera, Paolo Montuschi
2014	J	`jnl`	A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors. IEEE Embed. Syst. Lett. Maurizio Martina, Carlo Condo, Guido Masera, Maurizio Zamboni
2014	J	`jnl`	A Parallel Radix-Sort-Based VLSI Architecture for Finding the First W Maximum/Minimum Values. IEEE Trans. Circuits Syst. II Express Briefs Guoping Xiao, Maurizio Martina, Guido Masera, Gianluca Piccinini
2014	C	`conf`	A novel decoder architecture for error resilient JPEG2000 applications based on MQ arithmetic. ISCAS Simone Zezza, Guido Masera, Saeid Nooshabadi
2014	J	`jnl`	Energy-efficient multi-standard early stopping criterion for low-density-parity-check iterative decoding. IET Commun. Carlo Condo, Amer Baghdadi, Guido Masera
2014	—	`conf`	Molecular transistor circuits: From device model to circuit simulation. NANOARCH Ali Zahir, Syed Azhar Ali Zaidi, Azzurra Pulimeno, Mariagrazia Graziano, Danilo Demarchi, Guido Masera, Gianluca Piccinini
2014	C	`conf`	Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-Based Applications. PDP Carlo Condo, Maurizio Martina, Massimo Ruo Roch, Guido Masera
2014	J	`jnl`	Simplified Log-MAP Algorithm for Very Low-Complexity Turbo Decoder Hardware Architectures. IEEE Trans. Instrum. Meas. Maurizio Martina, Stylianos Papaharalabos, P. Takis Mathiopoulos, Guido Masera
2014	J	`jnl`	Unified turbo/LDPC code decoder architecture for deep-space communications. IEEE Trans. Aerosp. Electron. Syst. Carlo Condo, Guido Masera
2014	J	`jnl`	VLSI Implementation of a Non-Binary Decoder Based on the Analog Digital Belief Propagation. IEEE Trans. Signal Process. Maurizio Awais, Guido Masera, Maurizio Martina, Guido Montorsi
2014	J	`jnl`	Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced. IEEE Signal Process. Lett. Carlo Condo, Maurizio Martina, Gianluca Piccinini, Guido Masera
2013	J	`jnl`	A 2.63 Mbit/s VLSI Implementation of SISO Arithmetic Decoders for High Performance Joint Source Channel Codes. IEEE Trans. Circuits Syst. I Regul. Pap. Simone Zezza, Saeid Nooshabadi, Guido Masera
2013	C	`conf`	A Joint Communication and Application Simulator for NoC-Based Custom SoCs: LDPC and Turbo Codes Parallel Decoding Case Study. DSD Carlo Condo, Amer Baghdadi, Guido Masera
2013	J	`jnl`	Analysis on parallel implementations of fixed-complexity sphere decoder. Sci. China Inf. Sci. Bin Wu, Guido Masera
2013	—	`conf`	FPGA accelerator of Quasi cyclic EG-LDPC codes decoder for NAND flash memories. DASIP Syed Azhar Ali Zaidi, Muhammad Awais, Carlo Condo, Maurizio Martina, Guido Masera
2013	J	`jnl`	Improving Network-on-Chip-based Turbo Decoder Architectures. J. Signal Process. Syst. Maurizio Martina, Guido Masera
2013	J	`jnl`	Power Control for Crossbar-Based Input-Queued Switches. IEEE Trans. Computers Andrea Bianco, Paolo Giaccone, Guido Masera, Marco Ricca
2013	C	`conf`	VLSI Architecture for Low-Complexity Motion Estimation in H.264 Multiview Video Coding. DSD Ashfaq Ahmed, Muhammad Usman Shahid, Maurizio Martina, Enrico Magli, Guido Masera
2013	J	`jnl`	VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. Carlo Condo, Maurizio Martina, Guido Masera
2012	A	`conf`	A Network-on-Chip-based turbo/LDPC decoder architecture. DATE Carlo Condo, Maurizio Martina, Guido Masera
2012	J	`jnl`	A System View on Iterative MIMO Detection: Dynamic Sphere Detection versus Fixed Effort List Detection. VLSI Design Christina Gimmler-Dumont, Frank Kienle, Bin Wu, Guido Masera
2012	J	`jnl`	An LDPC Decoder Architecture for Wireless Sensor Network Applications. Sensors Andrea Dario Giancarlo Biroli, Maurizio Martina, Guido Masera
2012	J	`jnl`	An application specific instruction set processor based implementation for signal detection in multiple antenna systems. Microprocess. Microsystems M. Tamagnone, Maurizio Martina, Guido Masera
2012	J	`jnl`	Efficient VLSI implementation of soft-input soft-output fixed-complexity sphere decoder. IET Commun. Bin Wu, Guido Masera
2012	—	`conf`	FFT implementation using QCA. ICECS Muhammad Awais, Marco Vacca, Mariagrazia Graziano, Guido Masera
2012	J	`jnl`	Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation. VLSI Design Guido Masera, Amer Baghdadi, Frank Kienle, Christophe Moy
2012	J	`jnl`	High Speed Architectures for Finding the First two Maximum/Minimum Values. IEEE Trans. Very Large Scale Integr. Syst. Luca Gaetano Amarù, Maurizio Martina, Guido Masera
2012	J	`jnl`	Non-recursive max IET Commun. Stylianos Papaharalabos, Panayiotis Takis Mathiopoulos, Guido Masera, Maurizio Martina
2012	J	`jnl`	On Practical Implementation and Generalizations of max IEEE Trans. Instrum. Meas. Maurizio Martina, Guido Masera, Stylianos Papaharalabos, P. Takis Mathiopoulos, Fotios Gioulekas
2012	—	`conf`	Reducing the memory for iteration-exchanged information and border future metrics in the HomePlug AV turbo decoder implementation. ISTC Lorenzo Guerrieri, Paola Bisaglia, Maurizio Martina, Guido Masera
2011	J	`jnl`	A Flexible LDPC code decoder with a Network on Chip as underlying interconnect architecture CoRR Carlo Condo, Guido Masera
2011	C	`conf`	A Novel Architecture for Scalable, High Throughput, Multi-standard LDPC Decoder. DSD Muhammad Awais, Ashwani Singh, Emmanuel Boutillon, Guido Masera
2011	—	`conf`	A flexible NoC-based LDPC code decoder implementation and bandwidth reduction methods. DASIP Carlo Condo, Guido Masera
2011	J	`jnl`	Improving Network-on-Chip-based turbo decoder architectures CoRR Maurizio Martina, Guido Masera
2011	J	`jnl`	Look-ahead sphere decoding: algorithm and VLSI architecture. IET Commun. Micaela Troglia Gamba, Guido Masera
2011	J	`jnl`	Multiplierless Mumford and Shah Functional Implementation. Circuits Syst. Signal Process. Maurizio Martina, Guido Masera
2011	J	`jnl`	On chip interconnects for multiprocessor turbo decoding architectures. Microprocess. Microsystems Maurizio Martina, Guido Masera, Hazem Moussa, Amer Baghdadi
2011	—	`conf`	Scalable, High Throughput LDPC Decoder for WiMAX (802.16e) Applications. ACC (2) Muhammad Awais, Ashwani Singh, Guido Masera
2011	J	`jnl`	State Metric Compression Techniques for Turbo Decoder Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. Maurizio Martina, Guido Masera
2010	C	`conf`	A Novel VLSI Architecture of Fixed-Complexity Sphere Decoder. DSD Bin Wu, Guido Masera
2010	J	`jnl`	A Novel VLSI Architecture of Fixed-complexity Sphere Decoder CoRR Bin Wu, Guido Masera
2010	C	`conf`	ALOE-Based Flexible LDPC Decoder. DSD Ismael Gómez, Massimo Camatel, Jordi Bracke, Vuk Marojevic, Antoni Gelonch, Fabrizio Vacca, Guido Masera
2010	J	`jnl`	Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding. Microprocess. Microsystems Sergio Saponara, Maurizio Martina, Michele Casula, Luca Fanucci, Guido Masera
2010	J	`jnl`	Scalable low-complexity B-spline discrete wavelet transform architecture. IET Circuits Devices Syst. Maurizio Martina, Guido Masera, Gianluca Piccinini
2010	B	`conf`	Thermal Control for Crossbar-Based Input-Queued Switches. GLOBECOM Andrea Bianco, Paolo Giaccone, Guido Masera, Marco Ricca
2010	J	`jnl`	Turbo NOC: A Framework for the Design of Network-on-Chip-Based Turbo Decoder Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. Maurizio Martina, Guido Masera
2010	J	`jnl`	VLSI Architectures for WIMAX Channel Decoders CoRR Maurizio Martina, Guido Masera
2009	B	`conf`	A feasible VLSI engine for soft-input-soft-output for joint source channel codes. ICIP Simone Zezza, Guido Masera, Saeid Nooshabadi
2009	J	`jnl`	A new performance evaluation metric for sub-optimal iterative decoders. IEEE Commun. Lett. Ashwani Singh, Ali Al Ghouwayel, Guido Masera, Emmanuel Boutillon
2009	J	`jnl`	Decoding the Golden Code: A VLSI Design. IEEE Trans. Very Large Scale Integr. Syst. Barbara Cerato, Guido Masera, Emanuele Viterbo
2009	J	`jnl`	Efficient Implementation Techniques for Maximum Likelihood-Based Error Correction for JPEG2000. IEEE Trans. Circuits Syst. Video Technol. Simone Zezza, Saeid Nooshabadi, Maurizio Martina, Guido Masera
2009	J	`jnl`	FPGA implementation of time-frequency analysis algorithms for laser welding monitoring. Microprocess. Microsystems Andrea Molino, Maurizio Martina, Fabrizio Vacca, Guido Masera, Andrea Terreno, Giorgio Pasquettaz, Giuseppe D'Angelo
2009	C	`conf`	Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm. DSD Fabrizio Vacca, Guido Masera, Hazem Moussa, Amer Baghdadi, Michel Jézéquel
2009	—	`conf`	Look-Ahead Sphere Decoding: Algorithm and performance evaluation. ISWCS Micaela Troglia Gamba, Guido Masera
2009	J	`jnl`	On Optimal and Near-Optimal Turbo Decoding Using Generalized max* Operator. IEEE Commun. Lett. Stylianos Papaharalabos, P. Takis Mathiopoulos, Guido Masera, Maurizio Martina
2009	J	`jnl`	Turbo NOC: a framework for the design of Network On Chip based turbo decoder architectures CoRR Maurizio Martina, Guido Masera
2009	J	`jnl`	Vlsi Implementation of WiMAX Convolutional Turbo Code Encoder and Decoder. J. Circuits Syst. Comput. Maurizio Martina, Mario Nicola, Guido Masera
2008	J	`jnl`	A Flexible UMTS-WiMax Turbo Decoder Architecture. IEEE Trans. Circuits Syst. II Express Briefs Maurizio Martina, Mario Nicola, Guido Masera
2008	J	`jnl`	Corrections to "Multiplierless, Folded 9/7-5/3 Wavelet VLSI Architecture" [Sep 07 770-774]. IEEE Trans. Circuits Syst. II Express Briefs Maurizio Martina, Guido Masera
2008	J	`jnl`	Decoding the golden space-time trellis coded modulation. IEEE Commun. Lett. Barbara Cerato, Guido Masera, Emanuele Viterbo
2008	J	`jnl`	Design of a VLSI Decoder for Partially Structured LDPC Codes. Int. J. Digit. Multim. Broadcast. Fabrizio Vacca, Libero Dinoi, Guido Masera
2008	J	`jnl`	Enabling VLSI Processing Blocks for MIMO-OFDM Communications. VLSI Design Barbara Cerato, Guido Masera, Emanuele Viterbo
2008	B	`conf`	Error resilient JPEG2000 decoding for wireless applications. ICIP Simone Zezza, Maurizio Martina, Guido Masera, Saeid Nooshabadi
2008	J	`jnl`	Hardware design of a low complexity, parallel interleaver for WiMax duo-binary turbo decoding. IEEE Commun. Lett. Maurizio Martina, Mario Nicola, Guido Masera
2008	A	`conf`	VLSI implementation of SISO arithmetic decoders for joint source channel coding. DATE Simone Zezza, Guido Masera
2007	—	`conf`	Beyond 3G wireless communication system prototype. ACM Great Lakes Symposium on VLSI Alberto Dassatti, Simone Zezza, Mario Nicola, Guido Masera
2007	J	`jnl`	Decoding the Golden Code: a VLSI design CoRR Barbara Cerato, Guido Masera, Emanuele Viterbo
2007	—	`conf`	Flexible blocks for high throughput serially concatenated convolutional codes. ACM Great Lakes Symposium on VLSI Maurizio Martina, Guido Masera
2007	—	`conf`	Hardware architecture for matrix factorization in mimo receivers. ACM Great Lakes Symposium on VLSI Barbara Cerato, Guido Masera, Peter Nilsson
2007	J	`jnl`	Implementation of a Flexible LDPC Decoder. IEEE Trans. Circuits Syst. II Express Briefs Guido Masera, Federico Quaglio, Fabrizio Vacca
2007	J	`jnl`	Multiplierless, Folded 9/7- 5/3 Wavelet VLSI Architecture. IEEE Trans. Circuits Syst. II Express Briefs Maurizio Martina, Guido Masera
2007	—	`conf`	Real-time implementation of a time-frequency analysis scheme. ACM Great Lakes Symposium on VLSI Maurizio Martina, Andrea Terreno, Fabrizio Vacca, Andrea Molino, Guido Masera, Giuseppe D'Angelo, Giorgio Pasquettaz
2007	J	`jnl`	Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study CoRR Paolo Bernardi, Guido Masera, Federico Quaglio, Matteo Sonza Reorda
2006	—	`conf`	A VLSI Decoder for the Golden code. ICECS Barbara Cerato, Guido Masera, Emanuele Viterbo
2006	—	`conf`	A new approach to compress the configuration information of programmable devices. DATE Designers' Forum Maurizio Martina, Guido Masera, Andrea Molino, Fabrizio Vacca, Luca Sterpone, Massimo Violante
2006	—	`conf`	Design of Application Specific Processors for the Cached FFT Algorithm. ICASSP (3) Oguzhan Atak, Abdullah Atalar, Erdal Arikan, Harold Ishebabi, David Kammler, Gerd Ascheid, Heinrich Meyr, Mario Nicola, Guido Masera
2006	—	`conf`	Error correcting arithmetic coding for JPEG 2000: memory and performance analysis. MobiMedia Simone Zezza, Marco Grangetto, Maurizio Martina, Fabrizio Vacca, Guido Masera
2006	—	`conf`	Hardware co-processors for Real-Time and High-Quality H.264/AVC video coding. EUSIPCO Maurizio Martina, Guido Masera, Luca Fanucci, Sergio Saponara
2006	—	`conf`	Interconnection framework for high-throughput, flexible LDPC decoders. DATE Designers' Forum Federico Quaglio, Fabrizio Vacca, Cristiano Castellano, Alberto Tarable, Guido Masera
2006	B	`conf`	Low-Complexity Video Compression Combining Adaptive Multifoveation and Reuse of High-Resolution Information. ICIP Giorgio Pioppo, Rashid Ansari, Ashfaq A. Khokhar, Guido Masera
2006	J	`jnl`	Low-Complexity, Efficient 9/7 Wavelet Filters VLSI Implementation. IEEE Trans. Circuits Syst. II Express Briefs Maurizio Martina, Guido Masera
2006	Misc	`conf`	Mixed hardware-software testbed for IEEE-802.11n. TRIDENTCOM Mario Nicola, Alberto Dassatti, Guido Masera, Andrea Concil, Angelo Poloni
2006	J	`jnl`	Mumford and Shah Functional: VLSI Analysis and Implementation. IEEE Trans. Pattern Anal. Mach. Intell. Maurizio Martina, Guido Masera
2005	—	`conf`	Design and implementation of phase correlation based motion estimator. SoCC Andrea Molino, Fabrizio Vacca, Guido Masera
2005	—	`conf`	High Performance Channel Model Hardware Emulator for 802.11n. FPT Alberto Dassatti, Guido Masera, Mario Nicola, Andrea Concil, Angelo Poloni
2005	—	`conf`	Low-complexity, efficient 9/7 wavelet filters implementation. ICIP (3) Maurizio Martina, Guido Masera
2005	—	`conf`	Optimized CORDIC core for frequency-domain motion estimation. ICIP (3) Andrea Molino, Fabrizio Vacca, Guido Masera
2004	—	`conf`	A statistical model for estimating the effect of process variations on crosstalk noise. SLIP Maurizio Martina, Guido Masera
2004	J	`jnl`	An electromigration and thermal model of power wires for a priori high-level reliability prediction. IEEE Trans. Very Large Scale Integr. Syst. Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
2004	J	`jnl`	Effects of temperature in deep-submicron global interconnect optimization in future technology nodes. Microelectron. J. Mariagrazia Graziano, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
2004	A	`conf`	Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study. DATE Paolo Bernardi, Guido Masera, Federico Quaglio, Matteo Sonza Reorda
2003	—	`conf`	A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization. PATMOS M. Addino, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
2003	J	`jnl`	Coupled electro-thermal modeling and optimization of clock networks. Microelectron. J. Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
2003	—	`conf`	Effects of Temperature in Deep-Submicron Global Interconnect Optimization. PATMOS Mario R. Casu, Mariagrazia Graziano, Gianluca Piccinini, Guido Masera, Maurizio Zamboni
2003	J	`jnl`	Novel JPEG 2000 Compliant DWT and IWT VLSI Implementations. J. VLSI Signal Process. Maurizio Martina, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
2003	A	`conf`	Wireless sensor networks: a power-scalable motion estimation IP for hybrid video coding. FPGA Federico Quaglio, Maurizio Martina, Fabrizio Vacca, Guido Masera, Andrea Molino, Gianluca Piccinini, Maurizio Zamboni
2002	J	`jnl`	Architectural strategies for low-power VLSI turbo decoders. IEEE Trans. Very Large Scale Integr. Syst. Guido Masera, Marco Mazza, Gianluca Piccinini, Fabrizio Viglione, Maurizio Zamboni
2002	—	`conf`	Clock Distribution Network Optimization under Self-Heating and Timing Constraints. PATMOS Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, M. M. Prono, Maurizio Zamboni
2002	—	`conf`	Embedded IWT evaluation in reconfigurable wireless sensor network. ICECS Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni
2002	B	`conf`	Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor. FPL Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni
2002	Misc	`conf`	Reconfigurable DSP IP for multimedia applications. ICASSP Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni
2002	—	`conf`	System architecture for error-resilient, embedded JPEG2000 wireless delivery. DSP Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni
2001	—	`conf`	Hierarchical power supply noise evaluation for early power grid design prediction. SLIP Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
2001	—	`conf`	JPEG 2000: finite precision representation and hardware implications. ICECS Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni
2001	—	`conf`	Reconfigurable coprocessor based JPEG 2000 implementation. ICECS Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni
2001	Misc	`conf`	Switching Noise Analysis Framework For High Speed Logic Families. VLSI Design Marco Delaurenti, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
2001	A	`conf`	Synthesis of low-leakage PD-SOI circuits with body-biasing. ISLPED Mario R. Casu, Gianluca Piccinini, Guido Masera, Maurizio Zamboni
2000	A	`conf`	A 50 Mbit/s Iterative Turbo-Decoder. DATE Fabrizio Viglione, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni
2000	C	`conf`	A high accuracy-low complexity model for CMOS delays. ISCAS Mario Roberto Casu, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni
2000	—	`conf`	Noise Safety Design Methodologies. ISQED Mariagrazia Graziano, Marco Delaurenti, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
1999	—	`conf`	A Quantitative Approach to the Design of an Optimized Hardware Interpreter for Java Byte-Code. Applied Informatics Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni
1999	—	`conf`	A global optimization tool for CMOS logic circuits. ICECS Marco Delaurenti, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
1999	—	`conf`	New 2 Gbit/s CMOS I/O pads. Great Lakes Symposium on VLSI Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni
1999	J	`jnl`	VLSI architectures for turbo codes. IEEE Trans. Very Large Scale Integr. Syst. Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni
1998	—	`conf`	A 500 MHz 2d-DWT VLSI processor. EUSIPCO A. Brizio, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni
1996	—	`conf`	A 650 MHz pipelined MAC for DSP applications using a new clocking strategy. EUSIPCO F. Fraternali, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
1996	—	`conf`	A Parametrical Architecture for Reed-Solomon Decoders. Great Lakes Symposium on VLSI Mariana-Eugenia Petre, Guido Masera
1993	J	`jnl`	PROXIMA: PROlog eXecutIon MAchine. IEEE J. Solid State Circuits Livio Baldi, Pierluigi Civera, Angela Iurlaro, Guido Masera, Andrea Pagni, Gianluca Piccinini, Rinaldo Poluzzi, Massimo Ruo Roch, Maurizio Zamboni
1989	J	`jnl`	Encoded 16-PSK: a study for the receiver design. IEEE J. Sel. Areas Commun. Sergio Benedetto, Marco Ajmone Marsan, Guido Masera, Gabriella Olmo, Z. Zhang