Guido Araujo

146 papers A* 5A 9B 8C 24Misc 8Journal 49Unranked 42
YearRankTypeTitle / Venue / Authors
2025 C conf
A Distributed and Storage-Aware Approach to Large-Scale Cholesky Factorization.
SBAC-PAD
Carla Cusihuallpa, Rodrigo Ceccato, Sandro Rigo, Guido Araujo, Hervé Yviquel
2025 A* conf
Boosting Task Scheduling Data Locality with Low-latency, HW-accelerated Label Propagation.
MICRO
Lucas Morais, Juan Miguel De Haro Ruiz, Alfredo Goldman, Guido Araujo, Giacomo Pedretti, Jim Ignowski, Michael Frank, Xavier Martorell, Daniel Jiménez-González, Carlos Álvarez
2025 J jnl
Checkpointing fine-tuning for accelerating seismic applications in GPUs.
Int. J. High Perform. Comput. Appl.
Thiago Maltempi, Sandro Rigo, Márcio Machado Pereira, Hervé Yviquel, Gustavo Leite, Orlando Lee, Jessé Costa, Guido Araujo
2025 B conf
Maximizing Resource Utilization for Stencil Computing.
FPL
Pedro Henrique Di Francia Rosso, Guido Araujo
2025 B conf
Multi-FPGA Programming Using OpenMP.
FPL
Pedro Henrique Di Francia Rosso, Guido Araujo
2025 — conf
Scalable OpenMP Remote Offloading via Asynchronous MPI and Coroutine-Driven Communication.
Euro-Par (3)
Jhonatan Cléto, Guilherme Valarini, Márcio Machado Pereira, Guido Araujo, Hervé Yviquel
2025 J jnl
Using MLIR Transform to Design Sliced Convolution Algorithm.
CoRR
Victor Ferrari, Márcio Machado Pereira, Lucas Alvarenga, Gustavo Leite, Guido Araujo
2024 — conf
Combining Compression and Prefetching to Improve Checkpointing for Inverse Seismic Problems in GPUs.
Euro-Par (3)
Thiago Maltempi, Sandro Rigo, Márcio Machado Pereira, Hervé Yviquel, Jessé Costa, Guido Araujo
2024 J jnl
ConvBench: A Comprehensive Benchmark for 2D Convolution Primitive Evaluation.
CoRR
Lucas Alvarenga, Victor Ferrari, Rafael Souza, Márcio Machado Pereira, Guido Araujo
2024 C conf
DeepWave: A Software Stack for Parallelizing Deep Learning Models Used in Geophysics.
SBAC-PAD
Allan Pinto, Gustavo Leite, Márcio Machado Pereira, Hervé Yviquel, Sandro Rigo, Guido Araujo
2024 J jnl
Enabling HW-Based Task Scheduling in Large Multicore Architectures.
IEEE Trans. Computers
Lucas Morais, Carlos Álvarez, Daniel Jiménez-González, Juan Miguel De Haro Ruiz, Guido Araujo, Michael Frank, Alfredo Goldman, Xavier Martorell
2024 — conf
Integrating Multi-FPGA Acceleration to OpenMP Distributed Computing.
IWOMP
Pedro Henrique Di Francia Rosso, Lucian Petrica, Nusrat Jahan Lisa, Márcio Machado Pereira, Sandro Rigo, Hervé Yviquel, Vanderlei Bonato, Emilio Francesquini, Guido Araujo
2024 J jnl
Ion-molecule collision cross-section calculations using trajectory parallelization in distributed systems.
J. Parallel Distributed Comput.
Samuel Cajahuaringa, Leandro N. Zanotto, Sandro Rigo, Hervé Yviquel, Munir S. Skaf, Guido Araujo
2024 — conf
Towards an Optimized Heterogeneous Distributed Task Scheduler in OpenMP Cluster.
SC Workshops
Rémy Neveu, Rodrigo Ceccato, Gustavo Leite, Guido Araujo, Jose Manuel Monsalve Diaz, Hervé Yviquel
2023 J jnl
Advancing Direct Convolution Using Convolution Slicing Optimization and ISA Extensions.
ACM Trans. Archit. Code Optim.
Victor Ferrari, Rafael Cardoso Fernandes Sousa, Márcio Machado Pereira, Joao P. L. de Carvalho, José Nelson Amaral, José E. Moreira, Guido Araujo
2023 J jnl
Advancing Direct Convolution using Convolution Slicing Optimization and ISA Extensions.
CoRR
Victor Ferrari, Rafael C. F. Sousa, Márcio Machado Pereira, João P. L. de Carvalho, José Nelson Amaral, José E. Moreira, Guido Araujo
2023 J jnl
Fast Matrix Multiplication via Compiler-only Layered Data Reorganization and Intrinsic Lowering.
CoRR
Braedy Kuzma, Ivan Korostelev, João P. L. de Carvalho, José E. Moreira, Christopher Barton, Guido Araujo, José Nelson Amaral
2023 J jnl
Fast matrix multiplication via compiler-only layered data reorganization and intrinsic lowering.
Softw. Pract. Exp.
Braedy Kuzma, Ivan Korostelev, João P. L. de Carvalho, José E. Moreira, Christopher Barton, Guido Araujo, José Nelson Amaral
2023 J jnl
MassCCS: A High-Performance Collision Cross-Section Software for Large Macromolecular Assemblies.
J. Chem. Inf. Model.
Samuel Cajahuaringa, Daniel L. Z. Caetano, Leandro N. Zanotto, Guido Araujo, Munir S. Skaf
2023 J jnl
On the impact of mode transition on phased transactional memory performance.
J. Parallel Distributed Comput.
Catalina Munoz Morales, Bruno C. Honorio, Joao P. L. de Carvalho, Alexandro Baldassin, Guido Araujo
2023 J jnl
Source Matching and Rewriting for MLIR Using String-Based Automata.
ACM Trans. Archit. Code Optim.
Vinícius Couto Espindola, Luciano G. Zago, Hervé Yviquel, Guido Araujo
2023 J jnl
Tensor Slicing and Optimization for Multicore NPUs.
CoRR
Rafael C. F. Sousa, Márcio Machado Pereira, Yongin Kwon, Taeho Kim, Namsoon Jung, Chang Soo Kim, Michael Frank, Guido Araujo
2023 J jnl
Tensor slicing and optimization for multicore NPUs.
J. Parallel Distributed Comput.
Rafael C. F. Sousa, Márcio Machado Pereira, Yongin Kwon, Taeho Kim, Namsoon Jung, Chang Soo Kim, Michael Frank, Guido Araujo
2022 — conf
An OpenMP-only Linear Algebra Library for Distributed Architectures.
SBAC-PADW
Carla Cardoso, Hervé Yviquel, Guilherme Valarini, Gustavo Leite, Rodrigo Ceccato, Márcio Machado Pereira, Alan Souza, Guido Araujo
2022 — conf
Implementing the Broadcast Operation in a Distributed Task-based Runtime.
SBAC-PADW
Rodrigo Ceccato, Hervé Yviquel, Márcio Machado Pereira, Alan Souza, Guido Araujo
2022 B conf
Improving Convolution via Cache Hierarchy Tiling and Reduced Packing.
PACT
Victor Ferrari, Rafael C. F. Sousa, Márcio Machado Pereira, João P. L. de Carvalho, José Nelson Amaral, Guido Araujo
2022 C conf
Ion-Molecule Collision Cross-Section Simulation using Linked-cell and Trajectory Parallelization.
SBAC-PAD
Samuel Cajahuaringa, Leandro N. Zanotto, Daniel L. Z. Caetano, Sandro Rigo, Hervé Yviquel, Munir S. Skaf, Guido Araujo
2022 J jnl
Special Issue on Compiling for Accelerators.
IEEE Micro
Guido Araujo, Lucas Wanner
2022 — conf
The OpenMP Cluster Programming Model.
ICPP Workshops
Hervé Yviquel, Márcio Machado Pereira, Emilio Francesquini, Guilherme Valarini, Gustavo Leite, Pedro Henrique Di Francia Rosso, Rodrigo Ceccato, Carla Cusihualpa, Vitoria Dias, Sandro Rigo, Alan Souza, Guido Araujo
2022 J jnl
The OpenMP Cluster Programming Model.
CoRR
Hervé Yviquel, Márcio Machado Pereira, Emilio Francesquini, Guilherme Valarini, Gustavo Leite, Pedro Henrique Di Francia Rosso, Rodrigo Ceccato, Carla Cusihualpa, Vitoria Dias, Sandro Rigo, Alan Souza, Guido Araujo
2022 J jnl
Using Barrier Elision to Improve Transactional Code Generation.
ACM Trans. Archit. Code Optim.
Bruno Chinelato Honorio, João P. L. de Carvalho, Catalina Munoz Morales, Alexandro Baldassin, Guido Araujo
2021 — conf
Accelerating Graph Applications Using Phased Transactional Memory.
Euro-Par
Catalina Munoz Morales, Rafael Murari, Joao P. L. de Carvalho, Bruno Chinelato Honorio, Alexandro Baldassin, Guido Araujo
2021 C conf
Efficient Tensor Slicing for Multicore NPUs using Memory Burst Modeling.
SBAC-PAD
Rafael C. F. Sousa, Byungmin Jung, Jaehwa Kwak, Michael Frank, Guido Araujo
2021 Misc conf
Enabling OpenMP Task Parallelism on Multi-FPGAs.
FCCM
Ramon Nepomuceno, Renan Sterle, Guilherme Valarini, Márcio Machado Pereira, Hervé Yviquel, Guido Araujo
2021 J jnl
Enabling OpenMP Task Parallelism on Multi-FPGAs.
CoRR
Ramon Nepomuceno, Renan Sterle, Guilherme Valarini, Márcio Machado Pereira, Hervé Yviquel, Guido Araujo
2021 C conf
Improving Phased Transactional Memory via Commit Throughput and Capacity Estimation.
SBAC-PAD
Catalina Munoz Morales, Bruno C. Honorio, Alexandro Baldassin, Guido Araujo
2021 J jnl
KernelFaRer: Replacing Native-Code Idioms with High-Performance Library Calls.
ACM Trans. Archit. Code Optim.
João P. L. de Carvalho, Braedy Kuzma, Ivan Korostelev, José Nelson Amaral, Christopher Barton, José E. Moreira, Guido Araujo
2020 — conf
Acceleration Opportunities in Linear Algebra Applications via Idiom Recognition.
ICPE Companion
João P. L. de Carvalho, Braedy Kuzma, Guido Araujo
2020 A conf
Improving Transactional Code Generation via Variable Annotation and Barrier Elision.
IPDPS
João P. L. de Carvalho, Bruno C. Honorio, Alexandro Baldassin, Guido Araujo
2020 — conf
NV-PhTM: An Efficient Phase-Based Transactional System for Non-volatile Memory.
Euro-Par
Alexandro Baldassin, Rafael Murari, João P. L. de Carvalho, Guido Araujo, Daniel Castro, João Barreto, Paolo Romano
2020 C conf
OmpTracing: Easy Profiling of OpenMP Programs.
SBAC-PAD
Vitoria Pinho, Hervé Yviquel, Márcio Machado Pereira, Guido Araujo
2020 — conf
Using OpenMP to Detect and Speculate Dynamic DOALL Loops.
IWOMP
Bruno Chinelato Honorio, João P. L. de Carvalho, Munir S. Skaf, Guido Araujo
2019 A* conf
Adding Tightly-Integrated Task Scheduling Acceleration to a RISC-V Multi-core Processor.
MICRO
Lucas Morais, Vitor Silva, Alfredo Goldman, Carlos Álvarez, Jaume Bosch, Michael Frank, Guido Araujo
2019 J jnl
Data-flow analysis and optimization for data coherence in heterogeneous architectures.
J. Parallel Distributed Comput.
Rafael C. F. Sousa, Márcio Machado Pereira, Fernando Magno Quintão Pereira, Guido Araujo
2019 J jnl
The Case for Phase-Based Transactional Memory.
IEEE Trans. Parallel Distributed Syst.
Joao P. L. de Carvalho, Guido Araujo, Alexandro Baldassin
2018 Misc conf
Automatic Offloading of Cluster Accelerators.
FCCM
Ciro Ceissler, Ramon Nepomuceno, Márcio Machado Pereira, Guido Araujo
2018 C conf
Automatic Ray-Tracer Cloud Offloading in OPENMP.
SBAC-PAD
Matheus Mortatti, Hervé Yviquel, Guido Araujo
2018 J jnl
CRPUF: A modeling-resistant delay PUF based on cylindrical reconvergence.
Microprocess. Microsystems
Rodrigo C. Surita, Mario Lúcio Côrtes, Diego F. Aranha, Guido Araujo
2018 J jnl
Cluster Programming using the OpenMP Accelerator Model.
ACM Trans. Archit. Code Optim.
Hervé Yviquel, Lauro Cruz, Guido Araujo
2018 C conf
DOACROSS Parallelization Based on Component Annotation and Loop-Carried Probability.
SBAC-PAD
Luis Mattos, Divino Cesar S. Lucas, Juan Salamanca, Joao P. L. de Carvalho, Márcio Machado Pereira, Guido Araujo
2018 J jnl
High performance collision cross section calculation - HPCCS.
J. Comput. Chem.
Leandro Zanotto, Gabriel Heerdt, Paulo C. T. Souza, Guido Araujo, Munir S. Skaf
2018 J jnl
Using Hardware-Transactional-Memory Support to Implement Thread-Level Speculation.
IEEE Trans. Parallel Distributed Syst.
Juan Salamanca, José Nelson Amaral, Guido Araujo
2017 — conf
Automatic Scan Parallelization in OpenMP.
SBAC-PAD (Workshops)
Maicol Zegarra, Márcio Machado Pereira, Xavier Martorell, Guido Araujo
2017 — conf
Compiling and Optimizing OpenMP 4.X Programs to OpenCL and SPIR.
IWOMP
Márcio Machado Pereira, Rafael C. F. Sousa, Guido Araujo
2017 C conf
Data Coherence Analysis and Optimization for Heterogeneous Computing.
SBAC-PAD
Rafael Cardoso Fernandes Sousa, Márcio Machado Pereira, Fernando Magno Quintão Pereira, Guido Araujo
2017 J jnl
DawnCC: Automatic Annotation for Data Parallelism and Offloading.
ACM Trans. Archit. Code Optim.
Gleison Souza Diniz Mendonca, Breno Campos Ferreira Guimarães, Péricles Alves, Márcio Machado Pereira, Guido Araujo, Fernando Magno Quintão Pereira
2017 — conf
Performance Evaluation of Thread-Level Speculation in Off-the-Shelf Hardware Transactional Memories.
Euro-Par
Juan Salamanca, José Nelson Amaral, Guido Araujo
2017 A conf
Revisiting phased transactional memory.
ICS
Joao P. L. de Carvalho, Guido Araujo, Alexandro Baldassin
2017 B conf
The Cloud as an OpenMP Offloading Device.
ICPP
Hervé Yviquel, Guido Araujo
2016 C conf
Automatic Insertion of Copy Annotation in Data-Parallel Programs.
SBAC-PAD
Gleison Souza Diniz Mendonca, Breno Campos Ferreira Guimarães, Péricles Rafael Oliveira Alves, Fernando Magno Quintão Pereira, Márcio Machado Pereira, Guido Araujo
2016 C conf
Cylindrical Reconvergence Physical Unclonable Function.
DSD
Rodrigo C. Surita, Mario Lúcio Côrtes, Diego F. Aranha, Guido Araujo
2016 A conf
Evaluating and Improving Thread-Level Speculation in Hardware Transactional Memories.
IPDPS
Juan Salamanca, José Nelson Amaral, Guido Araujo
2016 C conf
Parallel Computation for the All-Pairs Suffix-Prefix Problem.
SPIRE
Felipe A. Louza, Simon Gog, Leandro Zanotto, Guido Araujo, Guilherme P. Telles
2016 J jnl
Study of hardware transactional memory characteristics and serialization policies on Haswell.
Parallel Comput.
Márcio Machado Pereira, Matthew Gaudet, José Nelson Amaral, Guido Araujo
2016 — conf
Task parallel programming model + hardware acceleration = performance advantage.
Hot Chips Symposium
Tamer Dallou, Divino Cesar Soares Lucas, Guido Araujo, Lucas Morais, Eduardo Ferreira Barbosa, Michael Frank, Richard Bagley, Raj Sayana
2015 Misc conf
Computer security by hardware-intrinsic authentication.
CODES+ISSS
Caio Hoffman, Mario Lúcio Côrtes, Diego F. Aranha, Guido Araujo
2015 J jnl
Guest Editorial: SBAC-PAD 2013.
Int. J. Parallel Program.
Guido Araujo, Jean-Luc Gaudiot, Manish Parashar, Derek Chiou, José Nelson Amaral, Chita R. Das
2015 — conf
Improving the Statistical Variability of Delay-based Physical Unclonable Functions.
SBCCI
Jefferson Capovilla, Mario Lúcio Côrtes, Guido Araujo
2015 B conf
Performance implications of dynamic memory allocators on transactional memory systems.
PPoPP
Alexandro Baldassin, Edson Borin, Guido Araujo
2015 C conf
Serialization Management for Best-Effort Hardware Transactional Memory.
SBAC-PAD
Matthew Gaudet, Guido Araujo, José Nelson Amaral
2015 — conf
The Batched DOACROSS loop parallelization algorithm.
HPCS
Divino Cesar S. Lucas, Guido Araujo
2015 — conf
Using Hardware Transactional Memory to Enable Speculative Trace Optimization.
SBAC-PAD (Workshops)
Juan Salamanca, José Nelson Amaral, Guido Araujo
2014 C conf
Cloud-based OpenMP Parallelization Using a MapReduce Runtime.
SBAC-PAD
Rodolfo Wottrich, Rodolfo Azevedo, Guido Araujo
2014 — conf
Loop-Carried Dependence Verification in OpenMP.
IWOMP
Juan Salamanca, Luis Mattos, Guido Araujo
2014 B conf
Measuring Effective Work to Reward Success in Dynamic Transaction Scheduling.
ICPP
Márcio Machado Pereira, José Nelson Amaral, Guido Araujo
2014 J jnl
Microcode Compression Using Structured-Constrained Clustering.
Int. J. Parallel Program.
Edson Borin, Guido Araujo, Maurício Breternitz Jr., Youfeng Wu
2014 C conf
Multi-dimensional Evaluation of Haswell's Transactional Memory Performance.
SBAC-PAD
Márcio Machado Pereira, Matthew Gaudet, José Nelson Amaral, Guido Araujo
2014 A conf
Wear-out analysis of Error Correction Techniques in Phase-Change Memory.
DATE
Caio Hoffman, Luiz Ramos, Rodolfo Azevedo, Guido Araujo
2013 Misc conf
Cache-based cross-iteration coherence for speculative parallelization.
HiPC
Andre Baixo, João Paulo Porto, Guido Araujo
2013 J jnl
Extending decoupled software pipeline to parallelize Java programs.
Softw. Pract. Exp.
André Loureiro, João Paulo Porto, Guido Araujo
2013 — conf
Modeling virtual machines misprediction overhead.
IISWC
Divino Cesar S. Lucas, Rafael Auler, Rafael Dalibera, Sandro Rigo, Edson Borin, Guido Araujo
2013 J jnl
Transaction Scheduling Using Dynamic Conflict Avoidance.
Int. J. Parallel Program.
Daniel Nicácio, Alexandro Baldassin, Guido Araujo
2013 Misc conf
Transaction scheduling using conflict avoidance and Contention Intensity.
HiPC
Márcio Machado Pereira, Alexandro Baldassin, Guido Araujo, Luiz Eduardo Buzato
2012 J jnl
Computational reflection and its application to platform verification.
Des. Autom. Embed. Syst.
Bruno C. Albertini, Sandro Rigo, Guido Araujo
2012 — conf
Exploring Dynamic Program Behavior with Frames and Phases.
WSCAD-SSC
Divino Cesar S. Lucas, Guido Araujo, Edson Borin
2011 — conf
LUTS: A Lightweight User-Level Transaction Scheduler.
ICA3PP (1)
Daniel Nicácio, Alexandro Baldassin, Guido Araujo
2011 C conf
Structure-Constrained Microcode Compression.
SBAC-PAD
Edson Borin, Guido Araujo, Maurício Breternitz Jr., Youfeng Wu
2010 — conf
ISAMAP: Instruction Mapping Driven by Dynamic Binary Translation.
ISCA Workshops
Maxwell Souza, Daniel Nicácio, Guido Araujo
2010 — ed.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2010, São Paulo, Brazil, September 6-9, 2010
SBCCI
João Antonio Martino, Guido Araujo, Alex Orailoglu, Felipe Klein
2010 — conf
Reducing False Aborts in STM Systems.
ICA3PP (1)
Daniel Nicácio, Guido Araujo
2010 A conf
T-DRE: a hardware trusted computing base for direct recording electronic vote machines.
ACSAC
Roberto Gallo, Henrique Kawakami, Ricardo Dahab, Rafael Azevedo, Saulo Lima, Guido Araujo
2010 — conf
Trace Execution Automata in Dynamic Binary Translation.
ISCA Workshops
João Paulo Porto, Guido Araujo, Edson Borin, Youfeng Wu
2009 J jnl
A Multi-Model Engine for High-Level Power Estimation Accuracy Optimization.
IEEE Trans. Very Large Scale Integr. Syst.
Felipe Klein, Roberto Leao, Guido Araujo, Luiz C. V. dos Santos, Rodolfo Azevedo
2009 J jnl
Characterizing the Energy Consumption of Software Transactional Memory.
IEEE Comput. Archit. Lett.
Alexandro Baldassin, Felipe Klein, Guido Araujo, Rodolfo Azevedo, Paulo Centoducatte
2009 — conf
On the energy-efficiency of software transactional memory.
SBCCI
Felipe Klein, Alexandro Baldassin, Guido Araujo, Paulo Centoducatte, Rodolfo Azevedo
2008 J jnl
Instruction Scheduling Based on Subgraph Isomorphism for a High Performance Computer Processor.
J. Univers. Comput. Sci.
Ricardo Santos, Rodolfo Azevedo, Guido Araujo
2007 J jnl
A Custom Instruction Approach for Hardware and Software Implementations of Finite Field Arithmetic over F
J. VLSI Signal Process.
Marcio Juliato, Guido Araujo, Julio López, Ricardo Dahab
2007 C conf
A Flexible Platform Framework for Rapid Transactional Memory Systems Prototyping and Evaluation.
IEEE International Workshop on Rapid System Prototyping
Fernando Kronbauer, Alexandro Baldassin, Bruno C. Albertini, Paulo Centoducatte, Sandro Rigo, Guido Araujo, Rodolfo Azevedo
2007 — conf
A Methodology and Toolset to Enable SystemC and VHDL Co-simulation.
ISVLSI
Richard Maciel, Bruno C. Albertini, Sandro Rigo, Guido Araujo, Rodolfo Azevedo
2007 Misc conf
A computational reflection mechanism to support platform debugging in SystemC.
CODES+ISSS
Bruno C. Albertini, Sandro Rigo, Guido Araujo, Cristiano C. de Araújo, Edna Barros, Willians Azevedo
2007 A conf
A multi-model power estimation engine for accuracy optimization.
ISLPED
Felipe Klein, Guido Araujo, Rodolfo Azevedo, Roberto Leao, Luiz C. V. dos Santos
2007 — conf
On the Limitations of Power Macromodeling Techniques.
ISVLSI
Felipe Klein, Guido Araujo, Rodolfo Azevedo, Roberto Leao, Luiz C. V. dos Santos
2007 — conf
The Image Forest Transform Architecture.
FPT
Fabio Augusto Cappabianco, Guido Araujo, Alexandre X. Falcão
2006 — conf
2D-VLIW: An Architecture Based on the Geometry of Computation.
ASAP
Ricardo Santos, Rodolfo Azevedo, Guido Araujo
2006 C conf
Clustering-Based Microcode Compression.
ICCD
Edson Borin, Maurício Breternitz Jr., Youfeng Wu, Guido Araujo
2006 A conf
Exploiting dynamic reconfiguration techniques: the 2D-VLIW approach.
IPDPS
Ricardo Santos, Rodolfo Azevedo, Guido Araujo
2006 J jnl
Offset assignment using simultaneous variable coalescing.
ACM Trans. Embed. Comput. Syst.
Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers
2006 A conf
Software-Based Transparent and Comprehensive Control-Flow Error Detection.
CGO
Edson Borin, Cheng Wang, Youfeng Wu, Guido Araujo
2005 J jnl
A SystemC-only design methodology and the CINE-IP multimedia platform.
Des. Autom. Embed. Syst.
Guido Araujo, Edna Barros, Elmar U. K. Melcher, Rodolfo Azevedo, Karina R. G. da Silva, Bruno O. Prado, Manoel Eusébio de Lima
2005 — conf
A custom instruction approach for hardware and software implementations of finite field arithmetic over F
FPT
Marcio Juliato, Guido Araujo, Julio César López-Hernández, Ricardo Dahab
2005 — conf
Design of a decompressor engine on a SPARC processor.
SBCCI
Eduardo Afonso Billo, Rodolfo Azevedo, Guido Araujo, Paulo Centoducatte, Eduardo Braulio Wanderley Netto
2005 J jnl
Dynamic binary control-flow errors detection.
SIGARCH Comput. Archit. News
Edson Borin, Cheng Wang, Youfeng Wu, Guido Araujo
2005 J jnl
Efficient datapath merging for partially reconfigurable architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Nahri Moreano, Edson Borin, Cid C. de Souza, Guido Araujo
2005 — conf
High-Level Switching Activity Prediction Through Sampled Monitored Simulation.
SoC
Felipe Klein, Rodolfo Azevedo, Guido Araujo
2005 J jnl
Platform designer: An approach for modeling multiprocessor platforms based on SystemC.
Des. Autom. Embed. Syst.
Cristiano C. de Araújo, Millena Gomes, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Araujo
2005 C conf
Processor Centric Specification and Modelling of MPSoCs.
FDL
Cristiano C. de Araújo, Edna Barros, Rodolfo Azevedo, Guido Araujo
2005 J jnl
The ArchC Architecture Description Language and Tools.
Int. J. Parallel Program.
Rodolfo Azevedo, Sandro Rigo, Marcus Bartholomeu, Guido Araujo, Cristiano C. de Araújo, Edna Barros
2005 J jnl
The datapath merging problem in reconfigurable systems: Complexity, dual bounds and heuristic evaluation.
ACM J. Exp. Algorithmics
Cid C. de Souza, André M. Lima, Guido Araujo, Nahri Moreano
2004 — conf
An automatic testbench generation tool for a SystemC functional verification methodology.
SBCCI
Karina R. G. da Silva, Elmar U. K. Melcher, Guido Araujo, Valdiney Alves Pimenta
2004 C conf
ArchC: A SystemC-Based Architecture Description Language.
SBAC-PAD
Sandro Rigo, Guido Araujo, Marcus Bartholomeu, Rodolfo Azevedo
2004 — conf
Fast instruction set custornization.
ESTIMedia
Edson Borin, Felipe Klein, Nahri Moreano, Rodolfo Azevedo, Guido Araujo
2004 A conf
Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology.
DATE
Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Araujo
2004 C conf
Multi-Profile Instruction Based Compression.
SBAC-PAD
Eduardo Braulio Wanderley Netto, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo
2004 A* conf
Multi-profile based code compression.
DAC
Eduardo Braulio Wanderley Netto, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo
2004 C conf
Optimizations for Compiled Simulation Using Instruction Type Information.
SBAC-PAD
Marcus Bartholomeu, Rodolfo Azevedo, Sandro Rigo, Guido Araujo
2004 Misc conf
Teaching computer architecture using an architecture description language.
WCAE
Sandro Rigo, Marcio Juliato, Rodolfo Azevedo, Guido Araujo, Paulo Centoducatte
2004 — conf
The Datapath Merging Problem in Reconfigurable Systems: Lower Bounds and Heuristic Evaluation.
WEA
Cid C. de Souza, André M. Lima, Nahri Moreano, Guido Araujo
2004 J jnl
The design of dynamically reconfigurable datapath coprocessors.
ACM Trans. Embed. Comput. Syst.
Zhining Huang, Sharad Malik, Nahri Moreano, Guido Araujo
2003 J jnl
Address register allocation for arrays in loops of embedded programs.
Microelectron. J.
Guilherme Ottoni, Guido Araujo
2003 C conf
Exploring Memory Hierarchy with ArchC.
SBAC-PAD
Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Araujo
2003 C conf
Improving Offset Assignment through Simultaneous Variable Coalescing.
SCOPES
Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers
2003 — conf
Mixed static/dynamic profiling for dictionary based code compression.
SoC
Eduardo Braulio Wanderley Netto, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo
2002 — conf
Datapath Merging and Interconnection Sharing for Reconfigurable Architectures.
ISSS
Guido Araujo, Sharad Malik, Zhining Huang, Nahri Moreano
2002 J jnl
Global array reference allocation.
ACM Trans. Design Autom. Electr. Syst.
Guido Araujo, Guilherme Ottoni, Marcelo Silva Cintra
2001 J jnl
A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Subramanian Rajagopalan, Sreeranga P. Rajan, Sharad Malik, Sandro Rigo, Guido Araujo, Koichiro Takayama
2001 B conf
Optimal Live Range Merge for Address Register Allocation in Embedded Programs.
CC
Guilherme Ottoni, Sandro Rigo, Guido Araujo, Subramanian Rajagopalan, Sharad Malik
2001 Misc conf
Tailoring pipeline bypassing and functional unit mapping to application in clustered VLIW architectures.
CASES
Marcio Buss, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo
2000 B conf
Array Reference Allocation Using SSA-Form and Live Range Growth.
LCTES
Marcelo Silva Cintra, Guido Araujo
2000 J jnl
Expression-tree-based algorithms for code compression on embedded RISC architectures.
IEEE Trans. Very Large Scale Integr. Syst.
Guido Araujo, Paulo Centoducatte, Rodolfo Azevedo, Ricardo Pannain
1999 — conf
Compressed Code Execution on DSP Architectures.
ISSS
Paulo Centoducatte, Ricardo Pannain, Guido Araujo
1998 A* conf
Code Compression Based on Operand Factorization.
MICRO
Guido Araujo, Paulo Centoducatte, Mario Lúcio Côrtes, Ricardo Pannain
1998 J jnl
Code generation for fixed-point DSPs.
ACM Trans. Design Autom. Electr. Syst.
Guido Araujo, Sharad Malik
1996 — conf
Instruction Set Design and Optimizations for Address Computation in DSP Architectures.
ISSS
Guido Araujo, Ashok Sudarsanam, Sharad Malik
1996 A* conf
Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures.
DAC
Guido Araujo, Sharad Malik, Mike Tien-Chien Lee
1995 — conf
Optimal code generation for embedded memory non-homogeneous register architectures.
ISSS
Guido Araujo, Sharad Malik
1994 — conf
Challenges in code generation for embedded processors.
Code Generation for Embedded Processors
Guido Araujo, Srinivas Devadas, Kurt Keutzer, Stan Y. Liao, Sharad Malik, Ashok Sudarsanam, Steven W. K. Tjiang, Albert R. Wang