Guangyi Lu - RankMe

17 papers C 3Journal 11Unranked 3

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	Microwave Network-Assisted Analysis and Machine Learning-Assisted Synthesis of Arbitrarily Tapped Coils and Its Application to On-Chip Ultrawideband ESD Protection Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. JiaHao Wei, Weiqi Chen, Qi Wu, Guangyi Lu, Wei Gao, Lihui Wang, Mei Li, Haiming Wang
2023	J	`jnl`	Highly Efficient Automatic Synthesis of a Millimeter-Wave On-Chip Deformable Spiral Inductor Using a Hybrid Knowledge-Guided and Data-Driven Technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. JiaHao Wei, Weiqi Chen, Yajie Gong, Qi Wu, Guangyi Lu, Wei Gao, Lihui Wang, Mei Li, Haiming Wang
2020	J	`jnl`	A New Behavioral Model of Gate-Grounded NMOS for Simulating Snapback Characteristics. IEEE Access Yize Wang, Guangyi Lu, Yuan Wang
2018	C	`conf`	Investigation on the Gate Bias Voltage of BigFET in Power-rail ESD Clamp Circuit for Enhanced Transient Noise Immunity. ISCAS Guangyi Lu, Yuan Wang, Lizhong Zhang, Yize Wang, Ru Huang, Xing Zhang
2017	J	`jnl`	A novel TLP-based method to deliver IEC 61000-4-2 ESD stress. IEICE Electron. Express Yize Wang, Yuan Wang, Guangyi Lu, Jian Cao, Xing Zhang
2017	J	`jnl`	Power-Rail ESD Clamp Circuit with Parasitic-BJT and Channel Parallel Shunt Paths to Achieve Enhanced Robustness. IEICE Trans. Electron. Yuan Wang, Guangyi Lu, Yize Wang, Xing Zhang
2017	C	`conf`	Power-rail ESD clamp circuit with hybrid-detection enhanced triggering in a 65-nm, 1.2-V CMOS process. ISCAS Guangyi Lu, Yuan Wang, Yize Wang, Xing Zhang
2016	J	`jnl`	A compact SCR model using advanced BJT models and standard SPICE elements. Sci. China Inf. Sci. Jian Cao, Jingya Xu, Yuan Wang, Guangyi Lu, Xing Zhang
2016	J	`jnl`	A novel SPICE circuit model of electrostatic discharge (ESD) generator. IEICE Electron. Express Jian Cao, Yize Wang, Yuan Wang, Guangyi Lu, Xing Zhang
2016	C	`conf`	A novel low-leakage power-rail ESD clamp circuit with adjustable triggering voltage and superior false-triggering immunity for nanoscale applications. ISCAS Guangyi Lu, Yuan Wang, Jian Cao, Song Jia, Xing Zhang
2016	J	`jnl`	Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process. Sci. China Inf. Sci. Yuan Wang, Guangyi Lu, Haibing Guo, Jian Cao, Song Jia, Xing Zhang
2016	J	`jnl`	Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process. Sci. China Inf. Sci. Guangyi Lu, Yuan Wang, Lizhong Zhang, Jian Cao, Xing Zhang
2016	J	`jnl`	Optimization on Layout Strategy of Gate-Grounded NMOS for On-Chip ESD Protection in a 65-nm CMOS Process. IEICE Trans. Electron. Guangyi Lu, Yuan Wang, Xing Zhang
2015	—	`conf`	A low-leakage power clamp ESD protection circuit with prolonged ESD discharge time and compact detection network. ASICON Jian Cao, Zhenxu Ye, Yuan Wang, Guangyi Lu, Xing Zhang
2015	—	`conf`	Four-bit transient-to-digital converter with a single RC-based detection circuit for system-level ESD protection. ASICON Nan Han, Yuan Wang, Guangyi Lu, Jian Cao, Xing Zhang
2015	J	`jnl`	Investigation on the layout strategy of ggNMOS ESD protection devices for uniform conduction behavior and optimal width scaling. Sci. China Inf. Sci. Guangyi Lu, Yuan Wang, Lizhong Zhang, Jian Cao, Song Jia, Xing Zhang
2013	—	`conf`	Novel gate-voltage-bias techniques for gate-coupled MOS (GCMOS) ESD protection circuits. ASICON Guangyi Lu, Yuan Wang, Jian Cao, Song Jia, Ganggang Zhang, Xing Zhang