Guan-Ying Huang

19 papers C 3Journal 7Unranked 9
YearRankTypeTitle / Venue / Authors
2024 J jnl
Industrial federated learning algorithm (P-PFedSGD) for tool wear estimation.
Future Gener. Comput. Syst.
Guan-Ying Huang, Ching-Hung Lee
2021 — conf
Federated Learning Architecture for Bearing Fault Diagnosis.
ICSSE
Guan-Ying Huang, Ching-Hung Lee
2014 — conf
A 10b 100kS/s SAR ADC with charge recycling switching method.
A-SSCC
Kai-Hsiang Chiang, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin
2014 C conf
A 3.9-fJ/c.-s. 0.5-V 10-bit 100-kS/s low power SAR ADC with time-based fixed window.
ISCAS
Cheng-Hsun Ho, Soon-Jyh Chang, Guan-Ying Huang, Che-Hsun Kuo
2014 — conf
Low power pipelined SAR ADC with loading-free architecture.
VLSI-DAT
Jia-Jhang Wu, Soon-Jyh Chang, Sheng-Hsiung Lin, Chun-Po Huang, Guan-Ying Huang
2013 J jnl
10-bit 30-MS/s SAR ADC Using a Switchback Switching Method.
IEEE Trans. Very Large Scale Integr. Syst.
Guan-Ying Huang, Soon-Jyh Chang, Chun-Cheng Liu, Ying-Zu Lin
2013 J jnl
A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ying-Zu Lin, Chun-Cheng Liu, Guan-Ying Huang, Ya-Ting Shyu, Yen-Ting Liu, Soon-Jyh Chang
2013 — conf
A successive approximation ADC with resistor-capacitor hybrid structure.
VLSI-DAT
Ting-Zi Chen, Soon-Jyh Chang, Guan-Ying Huang
2012 J jnl
A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications.
IEEE J. Solid State Circuits
Guan-Ying Huang, Soon-Jyh Chang, Chun-Cheng Liu, Ying-Zu Lin
2012 J jnl
A Low-Cost Bit-Error-Rate BIST Circuit for High-Speed ADCs Based on Gray Coding.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Ya-Ting Shyu, Ying-Zu Lin, Rong-Sing Chu, Guan-Ying Huang, Soon-Jyh Chang
2012 — conf
A pipelined SAR ADC with loading-separating technique in 90-nm CMOS technology.
APCCAS
Sheng-Hsiung Lin, Jin-Fu Lin, Guan-Ying Huang, Soon-Jyh Chang
2012 C conf
A power-efficient sizing methodology of SAR ADCs.
ISCAS
Chun-Po Huang, Soon-Jyh Chang, Guan-Ying Huang, Cheng-Wu Lin
2011 — conf
A 0.9-V 11-bit 25-MS/s binary-search SAR ADC in 90-nm CMOS.
A-SSCC
Ying-Zu Lin, Soon-Jyh Chang, Ya-Ting Shyu, Guan-Ying Huang, Chun-Cheng Liu
2011 C conf
Building a Multi-kernel Embedded System with High Performance IPC Mechanism.
HPCC
Jing Chen, Da-Wei Chang, Chung-Ping Young, Guan-Ying Huang, Su-Lin Chu, Chung-Yuan Ke, Shih-Tun Yen, Tsang-Shuo Kuo
2010 J jnl
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure.
IEEE J. Solid State Circuits
Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin
2010 — conf
A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation.
ISSCC
Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin, Chung-Ming Huang, Chih-Hao Huang, Linkai Bu, Chih-Chung Tsai
2010 J jnl
An Asynchronous Binary-Search ADC Architecture With a Reduced Comparator Count.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu, Chun-Cheng Liu, Guan-Ying Huang
2010 — conf
Building Multi-kernel Embedded System on PAC Multi-core Platform.
QSIC
Jing Chen, Chung-Ping Young, Da-Wei Chang, Guan-Ying Huang, Chung-Yuan Ke, Shih-Tun Yen, Tsang-Shuo Kuo
2009 — conf
A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS.
ISSCC
Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu, Chun-Cheng Liu, Guan-Ying Huang