Grzegorz Pastuszak

43 papers A 2C 7Misc 1Journal 17Unranked 15
YearRankTypeTitle / Venue / Authors
2026 — conf
Ultra low zapping time with optimized I-frame delivery method for next-generation video streaming technologies.
MHV
Grzegorz Grzesiak, Michal Konarzewski, Marcin Bialek, Hobum Kwon, Grzegorz Pastuszak
2025 J jnl
On One-Parameter Families of Hermiticity-Preserving Superoperators which Are Not Positive.
Open Syst. Inf. Dyn.
Grzegorz Pastuszak, Alicja Jaworska-Pastuszak, Takeo Kamizawa
2025 J jnl
Optimization of Multisymbol Architecture of the Entropy Coder for H.265/HEVC Video Encoders.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Grzegorz Pastuszak
2021 J jnl
Quantifier elimination theory and maps which preserve semipositivity.
Quantum Inf. Process.
Grzegorz Pastuszak, Adam Skowyrski, Andrzej Jamiolkowski
2020 J jnl
Generative Multi-Symbol Architecture of the Binary Arithmetic Coder for UHDTV Video Encoders.
IEEE Trans. Circuits Syst. I Regul. Pap.
Grzegorz Pastuszak
2020 J jnl
Multisymbol Architecture of the Entropy Coder for H.265/HEVC Video Encoders.
IEEE Trans. Very Large Scale Integr. Syst.
Grzegorz Pastuszak
2016 J jnl
Algorithm and Architecture Design of the H.265/HEVC Intra Encoder.
IEEE Trans. Circuits Syst. Video Technol.
Grzegorz Pastuszak, Andrzej Abramowski
2016 J jnl
Algorithm and architecture design of the motion estimation for the H.265/HEVC 4K-UHD encoder.
J. Real Time Image Process.
Grzegorz Pastuszak, Maciej Trochimiuk
2016 J jnl
Architecture design of the high-throughput compensator and interpolator for the H.265/HEVC encoder.
J. Real Time Image Process.
Grzegorz Pastuszak, Maciej Trochimiuk
2016 J jnl
On a Criterion for Simultaneous Block-Diagonalization of Normal Matrices.
Open Syst. Inf. Dyn.
Grzegorz Pastuszak, Takeo Kamizawa, Andrzej Jamiolkowski
2016 J jnl
Optimization of the Adaptive Computationally-Scalable Motion Estimation and Compensation for the Hardware H.264/AVC Encoder.
J. Signal Process. Syst.
Grzegorz Pastuszak, Mariusz H. Jakubowski
2015 J jnl
Architecture Design of the H.264/AVC Encoder Based on Rate-Distortion Optimization.
IEEE Trans. Circuits Syst. Video Technol.
Grzegorz Pastuszak
2015 J jnl
Flexible Architecture Design for H.265/HEVC Inverse Transform.
Circuits Syst. Signal Process.
Grzegorz Pastuszak
2015 J jnl
Hardware architectures for the H.265/HEVC discrete cosine transform.
IET Image Process.
Grzegorz Pastuszak
2014 C conf
A double-path intra prediction architecture for the hardware H.265/HEVC encoder.
DDECS
Andrzej Abramowski, Grzegorz Pastuszak
2014 C conf
FPGA architectures of the quantization and the dequantization for video encoders.
DDECS
Grzegorz Pastuszak
2014 C conf
FPGA design of the computation unit for the semi-global stereo matching algorithm.
DDECS
Mikolaj Roszkowski, Grzegorz Pastuszak
2014 J jnl
Intra Prediction for the Hardware H.264/AVC High Profile Encoder.
J. Signal Process. Syst.
Mikolaj Roszkowski, Grzegorz Pastuszak
2013 C conf
A Novel Intra Prediction Architecture for the Hardware HEVC Encoder.
DSD
Andrzej Abramowski, Grzegorz Pastuszak
2013 J jnl
Adaptive Computationally Scalable Motion Estimation for the Hardware H.264/AVC Encoder.
IEEE Trans. Circuits Syst. Video Technol.
Grzegorz Pastuszak, Mariusz H. Jakubowski
2013 C conf
Architecture Design and Efficiency Evaluation for the High-Throughput Interpolation in the HEVC Encoder.
DSD
Grzegorz Pastuszak, Maciej Trochimiuk
2012 C conf
Hardware implementation of adaptive motion estimation and compensation for H.264/AVC.
PCS
Grzegorz Pastuszak, Mariusz H. Jakubowski
2010 — conf
Context-adaptive binary arithmetic decoder architecture for H.264/AVC.
PDeS
Andrzej Abramowski, Grzegorz Pastuszak
2010 — conf
Data Reuse in Two-level Hierarchical Motion Estimation for High Resolution Video Coding.
SIGMAP
Mariusz H. Jakubowski, Grzegorz Pastuszak
2010 — conf
Hardware implementation of the transformation module of the MPEG-4 AAC standard.
PDeS
Grzegorz Brzuchalski, Grzegorz Pastuszak
2010 — conf
Intra prediction hardware module for high-profile H.264/AVC decoder.
PDeS
Mikolaj Roszkowski, Grzegorz Pastuszak
2010 — conf
Stream header decoder and context-adaptive variable-length decoder hardware module for H.264/AVC codec.
PDeS
Grzegorz Pastuszak, Michal Wieczorek
2009 — conf
An Adaptive Computation-aware Algorithm for Multi-frame Variable Block-size Motion Estimation in H.264/AVC.
SIGMAP
Mariusz H. Jakubowski, Grzegorz Pastuszak
2008 J jnl
A High-Performance Architecture of the Double-Mode Binary Coder for H.264.AVC.
IEEE Trans. Circuits Syst. Video Technol.
Grzegorz Pastuszak
2008 — conf
Constant Bitrate Control for a Distributed Video Coding System.
SIGMAP
Mariusz H. Jakubowski, João Ascenso, Grzegorz Pastuszak
2008 — conf
Transforms and Quantization in the High-Throughput H.264/AVC Encoder Based on Advanced Mode Selection.
ISVLSI
Grzegorz Pastuszak
2007 — conf
Architecture Design of the Double-Mode Binarization for High-Profile H.264/AVC Compression.
SiPS
Grzegorz Pastuszak
2007 — conf
Multi-sequence H.264/AVC Rate Control Based on the Linear Model.
ICETE (Selected Papers)
Grzegorz Pastuszak, Andrzej Pietrasiewicz
2007 — conf
Rate Control for Multi-Sequence H.264/AVC Compression.
SIGMAP
Andrzej Pietrasiewicz, Grzegorz Pastuszak
2006 — ch.
A hardware-oriented analysis of arithmetic coding - comparative study of JPEG2000 and H.264/AVC comppression standards.
e-Business and Telecommunication Networks
Grzegorz Pastuszak
2006 C conf
Architecture Design for the Context Formatter in the H.264/AVC Encoder.
DDECS
Grzegorz Pastuszak
2006 — conf
Parallel Symbol Architectures for H.264/AVC Binary Coder Based on Arithmetic Coding.
PARELEC
Grzegorz Pastuszak
2005 A conf
A High-Performance Memory-Efficient Architecture of the Bit-Plane Coder in JPEG 2000.
ICME
Grzegorz Pastuszak
2005 J jnl
A high-performance architecture for embedded block coding in JPEG 2000.
IEEE Trans. Circuits Syst. Video Technol.
Grzegorz Pastuszak
2005 Misc conf
Efficient Hardware Architecture for EBCOT in JPEG 2000 Using a Feedback Loop from the Rate Controller to the Bit-Plane Coder.
ICIAP
Grzegorz Pastuszak
2004 — conf
A Novel Architecture of Arithmetic Coder in JPEG2000 Based on Parallel Symbol Encoding.
PARELEC
Grzegorz Pastuszak
2004 A conf
A high-performance architecture of arithmetic coder in JPEG2000.
ICME
Grzegorz Pastuszak
2004 — conf
Hardware-Oriented Analysis of the Arithmetic Coding - Comparative Study of JPEG2000 and H.264/AVC Compression Standards.
ICETE (3)
Grzegorz Pastuszak