Grzegorz Blakiewicz

18 papers C 2Journal 11Unranked 5
YearRankTypeTitle / Venue / Authors
2023 J jnl
Single-Slope ADC With Embedded Convolution Filter for Global-Shutter CMOS Image Sensors.
IEEE Trans. Circuits Syst. II Express Briefs
Miron Klosowski, Yichuang Sun, Waldemar Jendernalik, Grzegorz Blakiewicz, Jacek Jakusz, Stanislaw Szczepanski
2020 J jnl
A 1-nS 1-V Sub-1-µW Linear CMOS OTA with Rail-to-Rail Input for Hz-Band Sensory Interfaces.
Sensors
Jacek Jakusz, Waldemar Jendernalik, Grzegorz Blakiewicz, Miron Klosowski, Stanislaw Szczepanski
2020 J jnl
Light-Powered Starter for Micro-Power Boost DC-DC Converter for CMOS Image Sensors.
Circuits Syst. Signal Process.
Grzegorz Blakiewicz, Jacek Jakusz, Miron Klosowski, Waldemar Jendernalik, Stanislaw Szczepanski
2020 J jnl
Low-Power Receivers for Wireless Capacitive Coupling Transmission in 3-D-Integrated Massively Parallel CMOS Imager.
IEEE Trans. Circuits Syst. I Regul. Pap.
Grzegorz Blakiewicz, Miron Klosowski, Waldemar Jendernalik, Jacek Jakusz, Stanislaw Szczepanski
2018 J jnl
A High-Efficient Measurement System With Optimization Feature for Prototype CMOS Image Sensors.
IEEE Trans. Instrum. Meas.
Miron Klosowski, Jacek Jakusz, Waldemar Jendernalik, Grzegorz Blakiewicz, Stanislaw Szczepanski, Slawomir Koziel
2017 J jnl
A CMOS Pixel With Embedded ADC, Digital CDS and Gain Correction Capability for Massively Parallel Imaging Array.
IEEE Trans. Circuits Syst. I Regul. Pap.
Miron Klosowski, Waldemar Jendernalik, Jacek Jakusz, Grzegorz Blakiewicz, Stanislaw Szczepanski
2015 J jnl
A 0.5 V bulk-driven voltage follower/DC level shifter and its application in class AB output stage.
Int. J. Circuit Theory Appl.
Tomasz Kulej, Grzegorz Blakiewicz
2013 J jnl
An Analog Sub-Miliwatt CMOS Image Sensor With Pixel-Level Convolution Processing.
IEEE Trans. Circuits Syst. I Regul. Pap.
Waldemar Jendernalik, Grzegorz Blakiewicz, Jacek Jakusz, Stanislaw Szczepanski, Robert Piotrowski
2011 — conf
Analog CMOS processor for early vision processing with highly reduced power consumption.
ECCTD
Waldemar Jendernalik, Jacek Jakusz, Grzegorz Blakiewicz, Robert Piotrowski, Stanislaw Szczepanski
2011 J jnl
Output-capacitorless low-dropout regulator using a cascoded flipped voltage follower.
IET Circuits Devices Syst.
Grzegorz Blakiewicz
2010 J jnl
Frequency compensation for two-stage operational amplifiers with improved power supply rejection ratio characteristic.
IET Circuits Devices Syst.
Grzegorz Blakiewicz
2008 C conf
Optimization of active circuits for substrate noise suppression.
ISCAS
Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske
2007 J jnl
Supply current spectrum estimation of digital cores at early design.
IET Circuits Devices Syst.
Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske
2006 C conf
Estimation of supply current spectrum for early noise evaluation.
ISCAS
Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske
2005 — conf
Modeling of substrate noise block properties for early prediction.
ISCAS (3)
Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske
2005 — conf
Substrate noise modeling in early floorplanning of MS-SOCs.
ASP-DAC
Grzegorz Blakiewicz, Marcin Jeske, Malgorzata Chrzanowska-Jeske, Jin S. Zhang
2004 — conf
Substrate noise optimization in early floorplanning for mixed signal SOCs.
SoCC
Grzegorz Blakiewicz, Marcin Jeske, Malgorzata Chrzanowska-Jeske
2004 — conf
Substrate noise-aware floorplanning for mixed-signal SOCs.
ISCAS (2)
Marcin Jeske, Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske, Benyi Wang