Gregory Fredeman

12 papers Journal 7Unranked 5
YearRankTypeTitle / Venue / Authors
2021 J jnl
Cores, Cache, Content, and Characterization: IBM's Second Generation 14-nm Product, z15.
IEEE J. Solid State Circuits
David Wolpert, Christopher J. Berry, Brian Bell, Adam Jatkowski, Jesse Surprise, John Isakson, Ofer Geva, Brian Deskin, Mark Cichanowski, Dina Hamid, Chris Cavitt, Gregory Fredeman, Dinesh Kannambadi, Anthony Saporito, Ashutosh Mishra, Alper Buyuktosunoglu, Tobias Webel, Preetham Lobo, Ramon Bertran, Pradeep Bhadravati Parashurama, Dureseti Chidambarrao, Brandon Bruen, Alan P. Wagstaff, Eric Lukes, Sean M. Carey, Hunter F. Shi, Michael Romain, Paul Logsdon, Ishita Agarwal
2020 — conf
2.7 IBM z15: A 12-Core 5.2GHz Microprocessor.
ISSCC
Christopher J. Berry, Brian Bell, Adam Jatkowski, Jesse Surprise, John Isakson, Ofer Geva, Brian Deskin, Mark Cichanowski, Dina Hamid, Chris Cavitt, Gregory Fredeman, Anthony Saporito, Ashutosh Mishra, Alper Buyuktosunoglu, Tobias Webel, Preetham Lobo, Pradeep Parashurama, Ramon Bertran, Dureseti Chidambarrao, David Wolpert, Brandon Bruen
2020 J jnl
IBM z15: Physical design improvements to significantly increase content in the same technology.
IBM J. Res. Dev.
Christopher J. Berry, David Wolpert, Brian Bell, Adam Jatkowski, Jesse Surprise, Gerald Strevig, John Isakson, Ofer Geva, Brian Deskin, Mark Cichanowski, Giora Biran, Dina Hamid, Chris Cavitt, Gregory Fredeman, Dureseti Chidambarrao, Brandon Bruen, Michael H. Wood, Sean M. Carey, Drew Turner, Leon J. Sigal
2016 J jnl
A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access.
IEEE J. Solid State Circuits
Gregory Fredeman, Donald W. Plass, Abraham Mathews, Janakiraman Viraraghavan, Kenneth Reyer, Thomas J. Knips, Thomas Miller, Elizabeth L. Gerhard, Dinesh Kannambadi, Chris Paone, Dongho Lee, Daniel Rainey, Michael A. Sperling, Michael Whalen, Steven Burns, Rajesh Reddy Tummuru, Herbert Ho, Alberto Cestero, Norbert Arnold, Babar A. Khan, Toshiaki Kirihata, Subramanian S. Iyer
2015 — conf
17.4 A 14nm 1.1Mb embedded DRAM macro with 1ns access.
ISSCC
Gregory Fredeman, Donald W. Plass, Abraham Mathews, Kenneth Reyer, Thomas J. Knips, Thomas Miller, Elizabeth L. Gerhard, Dinesh Kannambadi, Chris Paone, Dongho Lee, Daniel Rainey, Michael A. Sperling, Michael Whalen, Steven Burns
2015 — conf
4.1 22nm Next-generation IBM System z microprocessor.
ISSCC
James D. Warnock, Brian W. Curran, John Badar, Gregory Fredeman, Donald W. Plass, Yuen H. Chan, Sean M. Carey, Gerard Salem, Friedrich Schroeder, Frank Malgioglio, Guenter Mayer, Christopher J. Berry, Michael H. Wood, Yiu-Hing Chan, Mark D. Mayo, John Isakson, Charudhattan Nagarajan, Tobias Werner, Leon J. Sigal, Ricardo Nigaglioni, Mark Cichanowski, Jeffrey A. Zitz, Matthew M. Ziegler, Tim Bronson, Gerald Strevig, Daniel Dreps, Ruchir Puri, Douglas Malone, Dieter F. Wendel, Pak-kin Mak, Michael A. Blake
2011 J jnl
A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache.
IEEE J. Solid State Circuits
John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael A. Sperling, Abraham Mathews, Toshiaki Kirihata, William R. Reohr, Kavita Nair, Nianzheng Cao
2010 — conf
A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache.
ISSCC
John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael A. Sperling, Abraham Mathews, William R. Reohr, Kavita Nair, Nianzheng Cao
2009 J jnl
A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.
IEEE J. Solid State Circuits
Peter J. Klim, John Barth, William R. Reohr, David Dick, Gregory Fredeman, Gary Koch, Hien M. Le, Aditya Khargonekar, Pamela Wilcox, John Golz, Jente B. Kuang, Abraham Mathews, Jethro C. Law, Trong Luong, Hung C. Ngo, Ryan Freese, Hillery C. Hunter, Erik Nelson, Paul C. Parries, Toshiaki Kirihata, Subramanian S. Iyer
2008 J jnl
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier.
IEEE J. Solid State Circuits
John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer
2007 — conf
A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier.
ISSCC
John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer
2005 J jnl
An 800-MHz embedded DRAM with a concurrent refresh mode.
IEEE J. Solid State Circuits
Toshiaki Kirihata, Paul C. Parries, David R. Hanson, Hoki Kim, John Golz, Gregory Fredeman, Raj Rajeevakumar, John Griesemer, Norman Robson, Alberto Cestero, Babar A. Khan, Geng Wang, Matt Wordeman, Subramanian S. Iyer