Gregorio Cappuccino

28 papers A 1C 3Journal 10Unranked 14
YearRankTypeTitle / Venue / Authors
2014 J jnl
Design of a 75-nW, 0.5-V subthreshold complementary metal-oxide-semiconductor operational amplifier.
Int. J. Circuit Theory Appl.
Luca Magnelli, Francesco A. Amoroso, Felice Crupi, Gregorio Cappuccino, Giuseppe Iannaccone
2012 J jnl
A new efficient SC integrator scheme for high-speed low-power applications.
Int. J. Circuit Theory Appl.
Francesco A. Amoroso, Andrea Pugliese, Gregorio Cappuccino
2012 J jnl
Design approach for high-bandwidth low-power three-stage operational amplifiers.
Int. J. Circuit Theory Appl.
Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo
2012 C conf
Special session: IEEE Real World Engineering Projects: Discovery-based curriculum modules for first-year students.
FIE
Stephen Williams, Anita N. Vasavada, Jacques Nicolas Beneat, Gregorio Cappuccino, David C. Lin, Warren A. Rosen, M. Eric Carr, Kirk Reinkens, Mingrui Zhang, Francesco A. Amoroso
2011 J jnl
Design criterion for high-speed low-power SC circuits.
Int. J. Circuit Theory Appl.
Francesco A. Amoroso, Andrea Pugliese, Gregorio Cappuccino
2010 J jnl
Analysis of op-amp phase margin impact on SC SigmaDelta modulator performance.
Microelectron. J.
Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo
2010 J jnl
Analysis of the Impact of High-Order Integrator Dynamics on SC Sigma-Delta Modulator Performances.
IEEE Trans. Circuits Syst. I Regul. Pap.
Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo
2010 J jnl
Corrections to "Settling Time Optimization for Three-Stage CMOS Amplifier Topologies" [Dec 09 2569-2582].
IEEE Trans. Circuits Syst. I Regul. Pap.
Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo
2009 — conf
Class-AB output stage design for high-speed three-stage op-amps.
ICECS
Gregorio Cappuccino, Francesco A. Amoroso, Andrea Pugliese
2009 — conf
Design considerations for fast-settling two-stage Miller-compensated operational amplifiers.
ICECS
Francesco A. Amoroso, Andrea Pugliese, Gregorio Cappuccino
2009 C conf
Effect of OP-amp Phase Margin on SC SigmaDelta Modulator Performances.
ISCAS
Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo
2009 J jnl
Settling Time Optimization for Three-Stage CMOS Amplifier Topologies.
IEEE Trans. Circuits Syst. I Regul. Pap.
Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo
2008 J jnl
Design Procedure for Settling Time Minimization in Three-Stage Nested-Miller Amplifiers.
IEEE Trans. Circuits Syst. II Express Briefs
Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo
2008 — conf
Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers.
PATMOS
Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo
2007 — conf
Design methodology of nested-Miller amplifiers for small capacitive loads.
ECCTD
Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo
2007 — conf
Integrated waveguides for ultra-high speed interconnects.
Nano-Net
Davide Urbano, Emilio Arnieri, Gregorio Cappuccino, Giandomenico Amendola
2007 — conf
Settling Time Minimization of Operational Amplifiers.
PATMOS
Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo
2006 — conf
A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion Technique.
PATMOS
Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo
2006 — conf
Correct Modelling of Nested Miller Compensated Amplifier for Discrete-Time Applications.
PATMOS
Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo
2005 — conf
Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation.
PATMOS
Gregorio Cappuccino, Andrea Pugliese, Giuseppe Cocorullo
2003 C conf
Operating Region Modelling of Deep-submicron CMOS Buffers Driving Global Scope Inductive Interconnects.
DSD
Gregorio Cappuccino
2003 — conf
Operating mode analysis of deep-submicron CMOS buffers driving inductive interconnects.
ICECS
Gregorio Cappuccino
2002 — conf
Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines.
PATMOS
Gregorio Cappuccino, Giuseppe Cocorullo
2001 A conf
CMOS sizing rule for high performance long interconnects.
DATE
Gregorio Cappuccino, Giuseppe Cocorullo
2001 — conf
Dynamic power of CMOS gates driving lossy transmission lines.
ICECS
Gregorio Cappuccino, Pasquale Corsonello, Giuseppe Cocorullo, Stefania Perri, Giovanni Staino
2001 — conf
VLSI implementation of a fully static CMOS 56-bit self-timed adder using overlapped execution circuits.
ICECS
Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo, Gregorio Cappuccino, Giovanni Staino
1999 — conf
A Time-Domain Model for Power Dissipation of CMOS Buffers Driving Lossy Transmission Lines.
EUROMICRO
Gregorio Cappuccino, Giuseppe Cocorullo
1998 J jnl
High performance VLSI modules for division and square root.
Microprocess. Microsystems
Gregorio Cappuccino, Pasquale Corsonello, Giuseppe Cocorullo