Gregg Baeckler

16 papers A* 1A 4B 2C 1Misc 2Journal 2Unranked 4

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	A 950 MHz SIMT Soft Processor. IPDPS (Workshops) Martin Langhammer, Gregg Baeckler, Kim Bozman
2025	J	`jnl`	A 950 MHz SIMT Soft Processor. CoRR Martin Langhammer, Gregg Baeckler, Kim Bozman
2025	—	`conf`	High Performance Soft Multi-Processor Arrays. ASAP Martin Langhammer, Gregg Baeckler, Kim Bozman
2020	Misc	`conf`	High Density 8-Bit Multiplier Systolic Arrays For Fpga. FCCM Martin Langhammer, Sergey Gribok, Gregg Baeckler
2020	A	`conf`	High Density Pipelined 8bit Multiplier Systolic Arrays for FPGA. FPGA Martin Langhammer, Sergey Gribok, Gregg Baeckler
2020	—	`conf`	SpiderWeb - High Performance FPGA NoC. IPDPS Workshops Martin Langhammer, Gregg Baeckler, Sergey Gribok
2019	B	`conf`	Extracting INT8 Multipliers from INT18 Multipliers. FPL Martin Langhammer, Bogdan Pasca, Gregg Baeckler, Sergey Gribok
2019	A	`conf`	Fractal Synthesis: Invited Tutorial. FPGA Martin Langhammer, Gregg Baeckler, Sergey Gribok
2019	J	`jnl`	High Performance Scalable FPGA Accelerator for Deep Neural Networks. CoRR Sudarshan Srinivasan, Pradeep Janedula, Saurabh Dhoble, Sasikanth Avancha, Dipankar Das, Naveen Mellempudi, Bharat Daga, Martin Langhammer, Gregg Baeckler, Bharat Kaul
2019	Misc	`conf`	High Precision, High Performance FPGA Adders. FCCM Martin Langhammer, Bogdan Pasca, Gregg Baeckler
2018	C	`conf`	High Density and Performance Multiplication for FPGA. ARITH Martin Langhammer, Gregg Baeckler
2016	A	`conf`	HyperPipelining of High-Speed Interface Logic. FPGA Gregg Baeckler
2006	—	`conf`	A methodology for FPGA to structured-ASIC synthesis and verification. DATE Designers' Forum Michael D. Hutton, Richard Yuan, Jay Schleicher, Gregg Baeckler, Sammy Cheung, Kar Keng Chua, Hee Kong Phoo
2006	A*	`conf`	Efficient SAT-based Boolean matching for FPGA technology mapping. DAC Sean Safarpour, Andreas G. Veneris, Gregg Baeckler, Richard Yuan
2005	A	`conf`	The Stratix II logic and routing architecture. FPGA David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose
2004	B	`conf`	Improving FPGA Performance and Area Using an Adaptive Logic Module. FPL Michael D. Hutton, Jay Schleicher, David M. Lewis, Bruce Pedersen, Richard Yuan, Sinan Kaptanoglu, Gregg Baeckler, Boris Ratchev, Ketan Padalia, Mark Bourgeault, Andy Lee, Henry Kim, Rahul Saini