Greg Yeric

30 papers A* 3A 8C 1Journal 10Unranked 8
YearRankTypeTitle / Venue / Authors
2022 J jnl
Design-Aware Partitioning-Based 3-D IC Design Flow With 2-D Commercial Tools.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kyungwook Chang, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
2022 — conf
Extreme Temperature (> 200 °C), Radiation Hard (> 1 Mrad), Dense (sub-50 nm CD), Fast (2 ns write pulses), Non-Volatile Memory Technology.
IMW
Saurabh V. Suryavanshi, Greg Yeric, Max Irby, X. M. Henry Huang, Glen Rosendale, Lucian Shifren
2021 J jnl
Device-to-System Performance Evaluation: from Transistor/Interconnect Modeling to VLSI Physical Design and Neural-Network Predictor.
CoRR
Chi-Shuen Lee, Brian Cline, Saurabh Sinha, Greg Yeric, H.-S. Philip Wong
2020 J jnl
Stack up your chips: Betting on 3D integration to augment Moore's Law scaling.
CoRR
Saurabh Sinha, Xiaoqing Xu, Mudit Bhargava, Shidhartha Das, Brian Cline, Greg Yeric
2019 — conf
IC Design After Moore's Law.
CICC
Greg Yeric
2019 J jnl
System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst.
Kyungwook Chang, Shidhartha Das, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
2018 J jnl
Standard Cell Library Design and Optimization Methodology for ASAP7 PDK.
CoRR
Xiaoqing Xu, Nishi Shah, Andrew Evans, Saurabh Sinha, Brian Cline, Greg Yeric
2017 C conf
DTCO for DSA-MP Hybrid Lithography with Double-BCP Materials in Sub-7nm Node.
ICCD
Jiaojiao Ou, Xiaoqing Xu, Brian Cline, Greg Yeric, David Z. Pan
2017 A conf
Frequency and time domain analysis of power delivery network for monolithic 3D ICs.
ISLPED
Kyungwook Chang, Shidhartha Das, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
2017 J jnl
Impact and Design Guideline of Monolithic 3-D IC at the 7-nm Technology Node.
IEEE Trans. Very Large Scale Integr. Syst.
Kyungwook Chang, Kartik Acharya, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
2017 A conf
Standard cell library design and optimization methodology for ASAP7 PDK: (Invited paper).
ICCAD
Xiaoqing Xu, Nishi Shah, Andrew Evans, Saurabh Sinha, Brian Cline, Greg Yeric
2016 J jnl
ASAP7: A 7-nm finFET predictive process design kit.
Microelectron. J.
Lawrence T. Clark, Vinay Vashishtha, Lucian Shifren, Aditya Gujja, Saurabh Sinha, Brian Cline, Chandarasekaran Ramamurthy, Greg Yeric
2016 — conf
At the core of system scaling.
ESSCIRC
Greg Yeric
2016 A conf
Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools.
ICCAD
Kyungwook Chang, Saurabh Sinha, Brian Cline, Raney Southerland, Michael Doherty, Greg Yeric, Sung Kyu Lim
2016 A conf
Four-tier Monolithic 3D ICs: Tier Partitioning Methodology and Power Benefit Study.
ISLPED
Kwang Min Kim, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
2016 A* conf
Match-making for monolithic 3D IC: finding the right technology node.
DAC
Kyungwook Chang, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
2016 — conf
Monolithic 3D IC design: Power, performance, and area impact at 7nm.
ISQED
Kartik Acharya, Kyungwook Chang, Bon Woong Ku, Shreepad Panth, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
2016 J jnl
Predicting future complementary metal-oxide-semiconductor technology - challenges and approaches.
IET Comput. Digit. Tech.
Robert C. Aitken, Vikas Chandra, Brian Cline, Shidhartha Das, David Pietromonaco, Lucian Shifren, Saurabh Sinha, Greg Yeric
2015 — conf
Circuit design perspectives for Ge FinFET at 10nm and beyond.
ISQED
Saurabh Sinha, Lucian Shifren, Vikas Chandra, Brian Cline, Greg Yeric, Robert C. Aitken, Bingjie Cheng, Andrew R. Brown, Craig Riddet, C. Alexandar, Campbell Millar, Asen Asenov
2015 A conf
Power benefit study of monolithic 3D IC at the 7nm technology node.
ISLPED
Kyungwook Chang, Kartik Acharya, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
2015 J jnl
Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu, David Z. Pan
2014 A conf
Design, technology and yield in the post-moore era.
ITC
Greg Yeric
2014 — conf
Physical design and FinFETs.
ISPD
Robert C. Aitken, Greg Yeric, Brian Cline, Saurabh Sinha, Lucian Shifren, Imran Iqbal, Vikas Chandra
2014 — conf
Self-aligned double patterning aware pin access and standard cell layout co-optimization.
ISPD
Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu, David Z. Pan
2013 — conf
The past present and future of design-technology co-optimization.
CICC
Greg Yeric, Brian Cline, Saurabh Sinha, David Pietromonaco, Vikas Chandra, Rob Aitken
2012 A conf
Design benchmarking to 7nm with FinFET predictive technology models.
ISLPED
Saurabh Sinha, Brian Cline, Greg Yeric, Vikas Chandra, Yu Cao
2012 A* conf
Exploring sub-20nm FinFET design with predictive technology models.
DAC
Saurabh Sinha, Greg Yeric, Vikas Chandra, Brian Cline, Yu Cao
2011 A conf
Correlating models and silicon for improved parametric yield.
DATE
Rob Aitken, Greg Yeric, David Flynn
2007 A* conf
Making Manufacturing Work For You.
DAC
Srikanth Venkataraman, Ruchir Puri, Steve Griffith, Ankush Oberai, Robert Madge, Greg Yeric, Walter Ng, Yervant Zorian
2005 J jnl
Infrastructure for Successful BEOL Yield Ramp, Transfer to Manufacturing, and DFM Characterization at 65 nm and Below.
IEEE Des. Test Comput.
Greg Yeric, Ethan Cohen, John Garcia, Kurt Davis, Esam Salem, Gary Green