Greg Stitt - RankMe

106 papers A* 1A 16B 6C 2Misc 16Journal 37Unranked 27

Year	Rank	Type	Title / Venue / Authors
2026	A	`conf`	Bridging the Gap: A Module-Context Modeling Methodology for Hyperscale FPGA Applications. FPGA Madison N. Emas, Austin Baylis, Greg Stitt
2026	A	`conf`	EdgeSort: A Sub-100 ns, Line-Rate FPGA Streaming Sorter. FPGA Greg Stitt, Wesley Piard, Christopher Crary
2025	J	`jnl`	Using FPGA devices to accelerate the evaluation phase of tree-based genetic programming: an extended analysis. Genet. Program. Evolvable Mach. Christopher Crary, Wesley Piard, Greg Stitt, Benjamin M. Hicks, Caleb Bean, Bogdan Burlacu, Wolfgang Banzhaf
2024	A	`conf`	Low-Latency, Line-Rate Variable-Length Field Parsing for 100+ Gb/s Ethernet. FPGA Greg Stitt, Wesley Piard, Christopher Crary
2024	J	`jnl`	Novel Toolset for Efficient Hardwired Micro-Op Translation in Embedded Microarchitectures. IEEE Embed. Syst. Lett. Kevin J. Phillipson, Michael G. Rywalt, Baibhab Chatterjee, Eric M. Schwartz, Greg Stitt
2023	Misc	`conf`	An Exploration of ATPG Methods for Redacted IP and Reconfigurable Hardware. VTS Jackson Fugate, Greg Stitt, Naren Vikram Raj Masna, Aritra Dasgupta, Swarup Bhunia, Nij Dorairaj, David Kehlet
2023	B	`conf`	Using FPGA Devices to Accelerate Tree-Based Genetic Programming: A Preliminary Exploration with Recent Technologies. EuroGP Christopher Crary, Wesley Piard, Greg Stitt, Caleb Bean, Benjamin M. Hicks
2022	Misc	`conf`	Work-in-Progress: Toward a Robust, Reconfigurable Hardware Accelerator for Tree-Based Genetic Programming. CASES Christopher Crary, Wesley Piard, Britton Chesley, Greg Stitt
2021	J	`jnl`	Dynamic Scheduling for Heterogeneous Multicores. SN Comput. Sci. Ruben Vazquez, Ayobami S. Edun, Ann Gordon-Ross, Greg Stitt
2021	—	`conf`	Scalable Performance Prediction of Irregular Workloads in Multi-Phase Particle-in-Cell Applications. IPDPS Workshops Sai P. Chenna, Herman Lam, Greg Stitt, S. Balachandar
2020	—	`conf`	FPGA Acceleration of Fluid-Flow Kernels. H2RC@SC Ryan Blanchard, Greg Stitt, Herman Lam
2020	J	`jnl`	PANDORA: An Architecture-Independent Parallelizing Approximation-Discovery Framework. ACM Trans. Embed. Comput. Syst. Greg Stitt, David Campbell
2019	—	`conf`	A FPGA-Pipelined, High-Throughput Approach to Coarse-Grained Simulation of HPC Systems. HPCS Carlo Pascoe, Ryan Blanchard, Herman Lam, Greg Stitt
2019	A	`conf`	Dynamic Scheduling on Heterogeneous Multicores. DATE Ayobami S. Edun, Ruben Vazquez, Ann Gordon-Ross, Greg Stitt
2019	C	`conf`	Energy Prediction for Cache Tuning in Embedded Systems. ICCD Ruben Vazquez, Ann Gordon-Ross, Greg Stitt
2019	—	`conf`	Machine Learning-based Prediction for Dynamic Architectural Optimizations. IGSC Ruben Vazquez, Ann Gordon-Ross, Greg Stitt
2019	—	`conf`	Machine Learning-based Prediction for Dynamic, Runtime Architectural Optimizations of Embedded Systems. NORCAS Ruben Vazquez, Ann Gordon-Ross, Greg Stitt
2019	—	`conf`	Multi-Parameter Performance Modeling using Symbolic Regression. HPCS Sai P. Chenna, Greg Stitt, Herman Lam
2019	Misc	`conf`	Offloading cache configuration prediction to an FPGA for hardware speedup and overhead reduction: work-in-progress. CODES+ISSS Ruben Vazquez, Ann Gordon-Ross, Greg Stitt
2019	B	`conf`	PANDORA: a parallelizing approximation-discovery framework (WIP paper). LCTES Greg Stitt, David Campbell
2019	—	`conf`	Seiba: An FPGA Overlay-Based Approach to Rapid Application Development. ReConFig David Wilson, Greg Stitt
2018	—	`conf`	A Recurrently Generated Overlay Architecture for Rapid FPGA Application Development. HEART David Wilson, Greg Stitt, James Coole
2018	Misc	`conf`	High-Frequency Absorption-FIFO Pipelining for Stratix 10 HyperFlex. FCCM Madison N. Emas, Austin Baylis, Greg Stitt
2018	B	`conf`	Scalable Behavioral Emulation of Extreme-Scale Systems Using Structural Simulation Toolkit. ICPP Ajay Ramaswamy, Nalini Kumar, Aravind Neelakantan, Herman Lam, Greg Stitt
2018	A	`conf`	Scalable Window Generation for the Intel Broadwell+Arria 10 and High-Bandwidth FPGA Systems. FPGA Greg Stitt, Abhay Gupta, Madison N. Emas, David Wilson, Austin Baylis
2017	J	`jnl`	A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance. Int. J. Reconfigurable Comput. David Wilson, Aniruddha Shastri, Greg Stitt
2017	J	`jnl`	A Scalable, Low-Overhead Finite-State Machine Overlay for Rapid FPGA Application Development. CoRR David Wilson, Greg Stitt
2017	J	`jnl`	A Uniquified Virtualization Approach to Hardware Security. IEEE Embed. Syst. Lett. Greg Stitt, Robert Karam, Kai Yang, Swarup Bhunia
2017	—	`conf`	Overlay-based side-channel countermeasures: A case study on correlated noise generation. MWSCAS Austin Baylis, Greg Stitt, Ann Gordon-Ross
2017	J	`jnl`	Serial Arithmetic Strategies for Improving FPGA Throughput. ACM Trans. Embed. Comput. Syst. Aaron Landy, Greg Stitt
2016	J	`jnl`	A Parallel Sliding-Window Generator for High-Performance Digital-Signal Processing on FPGAs. ACM Trans. Reconfigurable Technol. Syst. Greg Stitt, Eric Schwartz, Patrick Cooke
2016	—	`conf`	Behavioral Emulation for Scalable Design-Space Exploration of Algorithms and Architectures. ISC Workshops Nalini Kumar, Carlo Pascoe, Christopher Hajas, Herman Lam, Greg Stitt, Alan D. George
2016	A	`conf`	Doubling FPGA Throughput via a Soft SerDes Architecture for Full-Bandwidth Serial Pipelining (Abstract Only). FPGA Aaron Landy, Greg Stitt
2016	J	`jnl`	The Unified Accumulator Architecture: A Configurable, Portable, and Extensible Floating-Point Accumulator. ACM Trans. Reconfigurable Technol. Syst. David Wilson, Greg Stitt
2015	J	`jnl`	A Tradeoff Analysis of FPGAs, GPUs, and Multicores for Sliding-Window Applications. ACM Trans. Reconfigurable Technol. Syst. Patrick Cooke, Jeremy Fowers, Greg Brown, Greg Stitt
2015	—	`conf`	A scheduling and binding heuristic for high-level synthesis of fault-tolerant FPGA applications. ASAP Aniruddha Shastri, Greg Stitt, Eduardo Riccio
2015	Misc	`conf`	Adjustable-Cost Overlays for Runtime Compilation. FCCM James Coole, Greg Stitt
2015	—	`conf`	An interpolation-based approach to multi-parameter performance modeling for heterogeneous systems. ASAP Dylan Rudolph, Greg Stitt
2015	J	`jnl`	Core-Level Modeling and Frequency Prediction for DSP Applications on FPGAs. Int. J. Reconfigurable Comput. Gongyu Wang, Greg Stitt, Herman Lam, Alan D. George
2015	J	`jnl`	Finite-State-Machine Overlay Architectures for Fast FPGA Compilation and Application Portability. ACM Trans. Embed. Comput. Syst. Patrick Cooke, Lu Hao, Greg Stitt
2015	J	`jnl`	Low-Overhead FPGA Middleware for Application Portability and Productivity. ACM Trans. Reconfigurable Technol. Syst. Robert Kirchgessner, Alan D. George, Greg Stitt
2015	Misc	`conf`	Revisiting Serial Arithmetic: A Performance and Tradeoff Analysis for Parallel Applications on Modern FPGAs. FCCM Aaron Landy, Greg Stitt
2014	Misc	`conf`	A High Memory Bandwidth FPGA Accelerator for Sparse Matrix-Vector Multiplication. FCCM Jeremy Fowers, Kalin Ovtcharov, Karin Strauss, Eric S. Chung, Greg Stitt
2014	C	`conf`	A framework for dynamic parallelization of FPGA-accelerated applications. SCOPES Jeremy Fowers, Jianye Liu, Greg Stitt
2014	J	`jnl`	Fast, Flexible High-Level Synthesis from OpenCL using Reconfiguration Contexts. IEEE Micro James Coole, Greg Stitt
2013	—	`conf`	A comparison of correntropy-based feature tracking on FPGAs and GPUs. ASAP Patrick Cooke, Jeremy Fowers, Greg Stitt, Lee Hunt
2013	A	`conf`	A high-performance, low-energy FPGA accelerator for correntropy-based feature tracking (abstract only). FPGA Patrick Cooke, Jeremy Fowers, Lee Hunt, Greg Stitt
2013	J	`jnl`	A performance and energy comparison of convolution on GPUs, FPGAs, and multicore processors. ACM Trans. Archit. Code Optim. Jeremy Fowers, Greg Brown, John Robert Wernsing, Greg Stitt
2013	A	`conf`	Dynafuse: dynamic dependence analysis for FPGA pipeline fusion and locality optimizations. FPGA Jeremy Fowers, Greg Stitt
2013	—	`conf`	Pseudo-constant logic optimization. ASAP Aaron Landy, Greg Stitt
2013	—	`conf`	Virtual finite-state-machine architectures for fast compilation and portability. ASAP Lu Hao, Greg Stitt
2012	Misc	`conf`	A low-overhead interconnect architecture for virtual reconfigurable fabrics. CASES Aaron Landy, Greg Stitt
2012	A	`conf`	A performance and energy comparison of FPGAs, GPUs, and multicores for sliding-window applications. FPGA Jeremy Fowers, Greg Brown, Patrick Cooke, Greg Stitt
2012	Misc	`conf`	BPR: fast FPGA placement and routing using macroblocks. CODES+ISSS James Coole, Greg Stitt
2012	J	`jnl`	Bandwidth-Sensitivity-Aware Arbitration for FPGAs. IEEE Embed. Syst. Lett. Lu Hao, Greg Stitt
2012	A	`conf`	Communication visualization for bottleneck detection of high-level synthesis applications. FPGA John Curreri, Greg Stitt, Alan D. George
2012	J	`jnl`	Elastic computing: A portable optimization framework for hybrid computers. Parallel Comput. John Robert Wernsing, Greg Stitt
2012	B	`conf`	RACECAR: a heuristic for automatic function specialization on multi-core heterogeneous systems. PPoPP John Robert Wernsing, Greg Stitt
2012	J	`jnl`	RCML: An Environment for Estimation Modeling of Reconfigurable Computing Systems. ACM Trans. Embed. Comput. Syst. Casey Reardon, Brian Holland, Alan D. George, Greg Stitt, Herman Lam
2012	J	`jnl`	SCF: A Framework for Task-Level Coordination in Reconfigurable, Heterogeneous Systems. ACM Trans. Reconfigurable Technol. Syst. Vikas Aggarwal, Greg Stitt, Alan D. George, Changil Yoon
2012	Misc	`conf`	The RACECAR heuristic for automatic function specialization on multi-core heterogeneous systems. CASES John Robert Wernsing, Greg Stitt, Jeremy Fowers
2012	A	`conf`	VirtualRC: a virtual FPGA platform for applications and tools portability. FPGA Robert Kirchgessner, Greg Stitt, Alan D. George, Herman Lam
2011	J	`jnl`	An End-to-End Tool Flow for FPGA-Accelerated Scientific Computing. IEEE Des. Test Comput. Greg Stitt, Alan D. George, Herman Lam, Melissa C. Smith, Vikas Aggarwal, Gongyu Wang, Casey Reardon, Brian Holland, Seth Koehler, James Coole
2011	J	`jnl`	Are Field-Programmable Gate Arrays Ready for the Mainstream? IEEE Micro Greg Stitt
2011	J	`jnl`	High-Level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis. Int. J. Reconfigurable Comput. John Curreri, Greg Stitt, Alan D. George
2011	J	`jnl`	Intermediate Fabrics: Virtual Architectures for Near-Instant FPGA Compilation. IEEE Embed. Syst. Lett. Greg Stitt, James Coole
2011	J	`jnl`	Novo-G: At the Forefront of Scalable Reconfigurable Supercomputing. Comput. Sci. Eng. Alan D. George, Herman Lam, Greg Stitt
2011	J	`jnl`	Platform-aware bottleneck detection for reconfigurable computing applications. ACM Trans. Reconfigurable Technol. Syst. Seth Koehler, Greg Stitt, Alan D. George
2011	J	`jnl`	Thread Warping: Dynamic and Transparent Synthesis of Thread Accelerators. ACM Trans. Design Autom. Electr. Syst. Greg Stitt, Frank Vahid
2010	—	`conf`	A scalable performance prediction heuristic for implementation planning on heterogeneous systems. ESTIMedia John Robert Wernsing, Greg Stitt
2010	—	`conf`	An Automated Scheduling and Partitioning Algorithm for Scalable Reconfigurable Computing Systems. ERSA Casey Reardon, Alan D. George, Greg Stitt, Herman Lam
2010	B	`conf`	Elastic computing: a framework for transparent, portable, and adaptive multi-core heterogeneous computing. LCTES John Robert Wernsing, Greg Stitt
2010	—	`conf`	High-level synthesis techniques for in-circuit assertion-based verification. IPDPS Workshops John Curreri, Greg Stitt, Alan D. George
2010	Misc	`conf`	Intermediate fabrics: virtual architectures for circuit portability and fast placement and routing. CODES+ISSS James Coole, Greg Stitt
2010	—	`conf`	Novo-G: A View at the HPC Crossroads for Scientific Computing. ERSA Alan D. George, Herman Lam, Abhijeet Lawande, Carlo Pascoe, Greg Stitt
2010	—	`conf`	Performance modeling for multilevel communication in SHMEM+. PGAS Vikas Aggarwal, Changil Yoon, Alan D. George, Herman Lam, Greg Stitt
2010	—	`ed.`	Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2010, July 12-15, 2010, Las Vegas Nevada, USA ERSA Toomas P. Plaks, David Andrews, Ronald F. DeMara, Herman Lam, Jooheung Lee, Christian Plessl, Greg Stitt
2010	J	`jnl`	Traversal Caches: A Framework for FPGA Acceleration of Pointer Data Structures. Int. J. Reconfigurable Comput. James Coole, Greg Stitt
2009	—	`conf`	A Traversal Cache Framework for FPGA Acceleration of Pointer Data Structures: A Case Study on Barnes-Hut N-body Simulation. ReConFig James Coole, John Robert Wernsing, Greg Stitt
2009	—	`conf`	A framework for core-level modeling and design of reconfigurable computing algorithms. HPRCTA@SC Gongyu Wang, Greg Stitt, Herman Lam, Alan D. George
2009	—	`conf`	Bridging parallel and reconfigurable computing with multilevel PGAS and SHMEM+. HPRCTA@SC Vikas Aggarwal, Alan D. George, Kishore Yalamanchili, Changil Yoon, Herman Lam, Greg Stitt
2009	—	`conf`	SCF: a device- and language-independent task coordination framework for reconfigurable, heterogeneous systems. HPRCTA@SC Vikas Aggarwal, Rafael García, Greg Stitt, Alan D. George, Herman Lam
2008	A	`conf`	C is for circuits: capturing FPGA circuits as sequential code for portability. FPGA Scott Sirowy, Greg Stitt, Frank Vahid
2008	—	`conf`	Hardware/software partitioning with multi-version implementation exploration. ACM Great Lakes Symposium on VLSI Greg Stitt
2008	—	`conf`	Recursion flattening. ACM Great Lakes Symposium on VLSI Greg Stitt, Jason R. Villarreal
2008	Misc	`conf`	Traversal caches: a first step towards FPGA acceleration of pointer-based data structures. CODES+ISSS Greg Stitt, Gaurav Chaudhari, James Coole
2008	J	`jnl`	Warp Processing: Dynamic Translation of Binaries to FPGA Circuits. Computer Frank Vahid, Greg Stitt, Roman L. Lysecky
2007	J	`jnl`	A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms CoRR Greg Stitt, Frank Vahid
2007	J	`jnl`	Binary synthesis. ACM Trans. Design Autom. Electr. Syst. Greg Stitt, Frank Vahid
2007	Misc	`conf`	Thread warping: a framework for dynamic synthesis of thread accelerators. CODES+ISSS Greg Stitt, Frank Vahid
2006	A	`conf`	A code refinement methodology for performance-improved synthesis from C. ICCAD Greg Stitt, Frank Vahid, Walid A. Najjar
2006	J	`jnl`	Warp Processors. ACM Trans. Design Autom. Electr. Syst. Roman L. Lysecky, Greg Stitt, Frank Vahid
2005	A	`conf`	A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms. DATE Greg Stitt, Frank Vahid
2005	Misc	`conf`	Hardware/software partitioning of software binaries: a case study of H.264 decode. CODES+ISSS Greg Stitt, Frank Vahid, Gordon McGregor, Brian Einloth
2005	A	`conf`	Techniques for synthesizing binaries to an advanced register/memory structure. FPGA Greg Stitt, Zhi Guo, Walid A. Najjar, Frank Vahid
2004	J	`jnl`	Energy savings and speedups from partitioning critical software loops to hardware in embedded systems. ACM Trans. Embed. Comput. Syst. Greg Stitt, Frank Vahid, Shawn Nematbakhsh
2003	A*	`conf`	Dynamic hardware/software partitioning: a first approach. DAC Greg Stitt, Roman L. Lysecky, Frank Vahid
2003	J	`jnl`	Highly configurable platforms for embedded computing systems. Microelectron. J. Frank Vahid, Roman L. Lysecky, Chuanjun Zhang, Greg Stitt
2003	B	`conf`	Profiling tools for hardware/software partitioning of embedded applications. LCTES Dinesh C. Suresh, Walid A. Najjar, Frank Vahid, Jason R. Villarreal, Greg Stitt
2002	—	`conf`	Codesign-extended applications. CODES Brian Grattan, Greg Stitt, Frank Vahid
2002	J	`jnl`	Energy Advantages of Microprocessor Platforms with On-Chip Configurable Logic. IEEE Des. Test Comput. Greg Stitt, Frank Vahid
2002	A	`conf`	Hardware/software partitioning of software binaries. ICCAD Greg Stitt, Frank Vahid
2002	J	`jnl`	Improving Software Performance with Configurable Logic. Des. Autom. Embed. Syst. Jason R. Villarreal, Dinesh C. Suresh, Greg Stitt, Frank Vahid, Walid A. Najjar
2002	Misc	`conf`	Using On-Chip Configurable Logic to Reduce Embedded System Software Energy. FCCM Greg Stitt, Brian Grattan, Jason R. Villarreal, Frank Vahid
2001	J	`jnl`	Propagating constants past software to hardware peripherals in fixed-application embedded systems. SIGARCH Comput. Archit. News Frank Vahid, Rilesh Patel, Greg Stitt
2000	Misc	`conf`	A first-step towards an architecture tuning methodology for low power. CASES Greg Stitt, Frank Vahid, Tony Givargis, Roman L. Lysecky