Gracieli Posser

24 papers A 1C 3Journal 4Unranked 13

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Introduction to the Special Issue on Advances in Physical Design Automation. ACM Trans. Design Autom. Electr. Syst. Stephan Held, Gracieli Posser, Iris Hui-Ru Jiang, David G. Chinnery
2026	—	`ed.`	Proceedings of the 2026 International Symposium on Physical Design, ISPD 2026, BonnGermany, March 15-18, 2026 ISPD Stephan Held, Rickard Ewetz, Tung-Chieh Chen, Gracieli Posser
2025	—	`ed.`	Proceedings of the 2025 International Symposium on Physical Design, ISPD 2025, Austin, TX, USA, March 16-19, 2025 ISPD Gracieli Posser, Stephan Held
2024	—	`ed.`	Proceedings of the 2024 International Symposium on Physical Design, ISPD 2024, Taipei, Taiwan, March 12-15, 2024 ISPD Iris Hui-Ru Jiang, Gracieli Posser
2023	J	`jnl`	Introduction to the Special Section on Advances in Physical Design Automation. ACM Trans. Design Autom. Electr. Syst. Iris Hui-Ru Jiang, David G. Chinnery, Gracieli Posser, Jens Lienig
2022	—	`conf`	Challenges and Approaches in VLSI Routing. ISPD Gracieli Posser, Evangeline F. Y. Young, Stephan Held, Yih-Lang Li, David Z. Pan
2019	—	`conf`	ISPD 2019 Initial Detailed Routing Contest and Benchmark with Advanced Routing Rules. ISPD Wen-Hao Liu, Stefanus Mantik, Wing-Kai Chow, Yixiao Ding, Amin Farshidi, Gracieli Posser
2018	—	`conf`	ISPD 2018 Initial Detailed Routing Contest and Benchmarks. ISPD Stefanus Mantik, Gracieli Posser, Wing-Kai Chow, Yixiao Ding, Wen-Hao Liu
2016	J	`jnl`	Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar
2016	C	`conf`	Electromigration aware circuits by using special signal non-default routing rules. ISCAS Lucas de Paris, Gracieli Posser, Ricardo Reis
2016	C	`conf`	FinFET cells with different transistor sizing techniques against PVT variations. ISCAS Alexandra L. Zimpeck, Cristina Meinhardt, Gracieli Posser, Ricardo Augusto da Luz Reis
2016	—	`conf`	Reducing the number of transistors with gate clustering. LASCAS Calebe Conceição, Gracieli Posser, Ricardo Reis
2015	—	`conf`	Impact on performance, power, area and wirelength using electromigration-aware cells. ICECS Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar
2015	—	`conf`	Process variability in FinFET standard cells with different transistor sizing techniques. ICECS Alexandra L. Zimpeck, Cristina Meinhardt, Gracieli Posser, Ricardo Reis
2015	—	`conf`	Reducing the signal Electromigration effects on different logic gates by cell layout optimization. LASCAS Gracieli Posser, Lucas de Paris, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar
2014	A	`conf`	A systematic approach for analyzing and optimizing cell-internal signal electromigration. ICCAD Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar
2014	—	`conf`	Analyzing the electromigration effects on different metal layers and different wire lengths. ICECS Gracieli Posser, Vivek Mishra, Ricardo Augusto da Luz Reis, Sachin S. Sapatnekar
2014	J	`jnl`	Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Guilherme Flach, Tiago Reimann, Gracieli Posser, Marcelo O. Johann, Ricardo Reis
2014	—	`conf`	Perfomance Improvement with Dedicated Transistor Sizing for MOSFET and FinFET Devices. ISVLSI Gracieli Posser, Jozeanne Belomo, Cristina Meinhardt, Ricardo Augusto da Luz Reis
2013	C	`conf`	Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing. ISCAS Tiago Reimann, Gracieli Posser, Guilherme Flach, Marcelo O. Johann, Ricardo Reis
2013	—	`conf`	Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities. ISVLSI Guilherme Flach, Tiago Reimann, Gracieli Posser, Marcelo O. Johann, Ricardo Reis
2012	—	`conf`	Transistor sizing and gate sizing using geometric programming considering delay minimization. NEWCAS Gracieli Posser, Guilherme Flach, Gustavo Wilke, Ricardo Reis
2011	—	`conf`	Gate Sizing Minimizing Delay and Area. ISVLSI Gracieli Posser, Guilherme Flach, Gustavo Wilke, Ricardo Reis
2010	—	`conf`	A study on layout quality of automatic generated cells. ICECS Gracieli Posser, Adriel Ziesemer, Daniel Guimares Jr., Gustavo Wilke, Ricardo A. L. Reis