Grace Zgheib - RankMe

26 papers A 8B 8Misc 2Journal 3Unranked 4

Year	Rank	Type	Title / Venue / Authors
2026	A	`ed.`	Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2026, Seaside, CA, USA, February 22-24, 2026 FPGA Jing Li, Grace Zgheib
2025	Misc	`conf`	A Partitioning-Based CAD Flow for Interposer-Based Multi-Die FPGAs. FCCM Mahesh A. Iyer, Andrew B. Kahng, Jason Luu, Bodhisatta Pramanik, Kristofer Vorwerk, Grace Zgheib
2025	B	`conf`	ARC: A Runtime Engine for Accelerating Independent Multi-Agent Reinforcement Learning on Multi-Core Processors. ICPADS Samuel Wiggins, Nikunj Gupta, Grace Zgheib, Mahesh A. Iyer, Viktor K. Prasanna
2025	—	`conf`	Accelerating Independent Multi-Agent Reinforcement Learning on Multi-GPU Platforms. Euro-Par (3) Samuel Wiggins, Nikunj Gupta, Grace Zgheib, Mahesh A. Iyer, Viktor K. Prasanna
2025	B	`conf`	Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage. FPL Junius Pun, Xilai Dai, Grace Zgheib, Mahesh A. Iyer, Andrew Boutros, Vaughn Betz, Mohamed S. Abdelfattah
2025	J	`jnl`	Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage. CoRR Junius Pun, Xilai Dai, Grace Zgheib, Mahesh A. Iyer, Andrew Boutros, Vaughn Betz, Mohamed S. Abdelfattah
2022	J	`jnl`	Detailed Placement for Dedicated LUT-Level FPGA Interconnect. ACM Trans. Reconfigurable Technol. Syst. Stefan Nikolic, Grace Zgheib, Paolo Ienne
2021	B	`conf`	Clock Skew Scheduling: Avoiding the Runtime Cost of Mixed-Integer Linear Programming. FPL Grace Zgheib, Yu Shen Lu, Ilya Ganusov
2020	A	`conf`	Architectural Enhancements in Intel® Agilex™ FPGAs. FPGA Jeffrey Chromczak, Mark Wheeler, Charles Chiasson, Dana How, Martin Langhammer, Tim Vanderhoek, Grace Zgheib, Ilya Ganusov
2020	A	`conf`	Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing. FPGA Stefan Nikolic, Grace Zgheib, Paolo Ienne
2020	B	`conf`	Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths. FPL Stefan Nikolic, Grace Zgheib, Paolo Ienne
2019	B	`conf`	Finding a Needle in the Haystack of Hardened Interconnect Patterns. FPL Stefan Nikolic, Grace Zgheib, Paolo Ienne
2017	B	`conf`	Evaluating FPGA clusters under wide ranges of design parameters. FPL Grace Zgheib, Paolo Ienne
2017	—	`conf`	Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains. ACM Great Lakes Symposium on VLSI Zhufei Chu, Xifan Tang, Mathias Soeken, Ana Petkovska, Grace Zgheib, Luca Gaetano Amarù, Yinshui Xia, Paolo Ienne, Giovanni De Micheli, Pierre-Emmanuel Gaillardon
2017	—	`—`	Leading the Blind - Automated Transistor-Level Modeling for FPGA Architects. Grace Zgheib
2017	A	`conf`	NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element. FPGA Zhihong Huang, Xing Wei, Grace Zgheib, Wei Li, Yu Lin, Zhenghong Jiang, Kaihui Tu, Paolo Ienne, Haigang Yang
2016	—	`conf`	Automatic wire modeling to explore novel FPGA architectures. FPT Grace Zgheib, Paolo Ienne
2016	A	`conf`	FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures. FPGA Grace Zgheib, Manana Lortkipanidze, Muhsen Owaida, David Novo, Paolo Ienne
2015	B	`conf`	A technology mapper for depth-constrained FPGA logic cells. FPL Zhenghong Jiang, Grace Zgheib, Colin Yu Lin, David Novo, Zhihong Huang, Liqun Yang, Haigang Yang, Paolo Ienne
2015	Misc	`conf`	An Ant Colony Optimization Heuristic to Optimize Prediction of Stability of Object-Oriented Components. IRI Haidar M. Harmanani, Danielle Azar, Grace Zgheib, David Kozhaya
2015	J	`jnl`	Enhanced Technology Mapping for FPGAs with Exploration of Cell Configurations. J. Circuits Syst. Comput. Grace Zgheib, Iyad Ouaiss
2015	—	`conf`	Improved carry chain mapping for the VTR flow. FPT Ana Petkovska, Grace Zgheib, David Novo, Muhsen Owaida, Alan Mishchenko, Paolo Ienne
2014	A	`conf`	Revisiting and-inverter cones. FPGA Grace Zgheib, Liqun Yang, Zhihong Huang, David Novo, Hadi Parandeh-Afshar, Haigang Yang, Paolo Ienne
2013	A	`conf`	Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only). FPGA Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne
2013	B	`conf`	Shadow And-Inverter Cones. FPL Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne
2011	A	`conf`	Reducing the pressure on routing resources of FPGAs with generic logic chains. FPGA Hadi Parandeh-Afshar, Grace Zgheib, Philip Brisk, Paolo Ienne