Gordon R. Chiu

11 papers A 3B 1Journal 3Unranked 4

Year	Rank	Type	Title / Venue / Authors
2018	B	`conf`	DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration. FPL Mohamed S. Abdelfattah, David Han, Andrew Bitar, Roberto DiCecco, Shane O'Connell, Nitika Shanker, Joseph Chu, Ian Prins, Joshua Fender, Andrew C. Ling, Gordon R. Chiu
2018	J	`jnl`	DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration. CoRR Mohamed S. Abdelfattah, David Han, Andrew Bitar, Roberto DiCecco, Shane O'Connell, Nitika Shanker, Joseph Chu, Ian Prins, Joshua Fender, Andrew C. Ling, Gordon R. Chiu
2018	—	`conf`	Flexibility: FPGAs and CAD in Deep Learning Acceleration. ISPD Gordon R. Chiu, Andrew C. Ling, Davor Capalija, Andrew Bitar, Mohamed S. Abdelfattah
2018	—	`conf`	Harnessing Numerical Flexibility for Deep Learning on FPGAs. HEART Andrew C. Ling, Mohamed S. Abdelfattah, Shane O'Connell, Andrew Bitar, David Han, Roberto DiCecco, Suchit Subhaschandra, Chris N. Johnson, Dmitry Denisenko, Joshua Fender, Gordon R. Chiu
2017	J	`jnl`	An OpenCL(TM) Deep Learning Accelerator on Arria 10. CoRR Utku Aydonat, Shane O'Connell, Davor Capalija, Andrew C. Ling, Gordon R. Chiu
2017	A	`conf`	An OpenCL™ Deep Learning Accelerator on Arria 10. FPGA Utku Aydonat, Shane O'Connell, Davor Capalija, Andrew C. Ling, Gordon R. Chiu
2017	—	`conf`	Creating High Performance Applications with Intel's FPGA OpenCL™ SDK. IWOCL Andrew C. Ling, Utku Aydonat, Shane O'Connell, Davor Capalija, Gordon R. Chiu
2016	A	`conf`	The Stratix™ 10 Highly Pipelined FPGA Architecture. FPGA David M. Lewis, Gordon R. Chiu, Jeffrey Chromczak, David R. Galloway, Ben Gamsa, Valavan Manohararajah, Ian Milton, Tim Vanderhoek, John Van Dyken
2007	J	`jnl`	Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. IEEE Trans. Very Large Scale Integr. Syst. Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown
2006	—	`conf`	Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. SLIP Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown
2006	A	`conf`	Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs. ICCAD Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown