Gordon J. Brebner

64 papers A* 2A 5B 17C 1Misc 9Journal 9Unranked 17

Year	Rank	Type	Title / Venue / Authors
2022	A	`conf`	Blockchain Machine: A Network-Attached Hardware Accelerator for Hyperledger Fabric. ICDCS Haris Javaid, Ji Yang, Nathania Santoso, Mohit Upadhyay, Sundararajarao Mohan, Chengchen Hu, Gordon J. Brebner
2021	J	`jnl`	Blockchain Machine: A Network-Attached Hardware Accelerator for Hyperledger Fabric. CoRR Haris Javaid, Ji Yang, Nathania Santoso, Mohit Upadhyay, Sundararajarao Mohan, Chengchen Hu, Gordon J. Brebner
2020	J	`jnl`	Adaptable Switch: A Heterogeneous Switch Architecture for Network-Centric Computing. IEEE Commun. Mag. Siyi Qiao, Chengchen Hu, Gordon J. Brebner, Jianhua Zou, Xiaohong Guan
2019	Misc	`conf`	Event-Driven Packet Processing. HotNets Stephen Ibanez, Gianni Antichi, Gordon J. Brebner, Nick McKeown
2019	—	`conf`	FastProxy: Hardware and Software Acceleration of Stratum Mining Proxy. CVCBT Guanwen Zhong, Haris Javaid, Hassaan Saadat, Lingchao Xu, Chengchen Hu, Gordon J. Brebner
2019	B	`conf`	Optimizing Validation Phase of Hyperledger Fabric. MASCOTS Haris Javaid, Chengchen Hu, Gordon J. Brebner
2019	J	`jnl`	Optimizing Validation Phase of Hyperledger Fabric. CoRR Haris Javaid, Chengchen Hu, Gordon J. Brebner
2019	A	`conf`	The P4->NetFPGA Workflow for Line-Rate Packet Processing. FPGA Stephen Ibanez, Gordon J. Brebner, Nick McKeown, Noa Zilberman
2017	—	`conf`	Whippersnapper: A P4 Language Benchmark Suite. SOSR Huynh Tu Dang, Han Wang, Theo Jepsen, Gordon J. Brebner, Changhoon Kim, Jennifer Rexford, Robert Soulé, Hakim Weatherspoon
2015	—	`ed.`	Proceedings of the Eleventh ACM/IEEE Symposium on Architectures for networking and communications systems, ANCS 2015, Oakland, CA, USA, May 7-8, 2015 ANCS Gordon J. Brebner, Alex Bachmutsky, Chita R. Das
2015	—	`conf`	Programmable hardware for high performance SDN. OFC Gordon J. Brebner
2015	—	`conf`	Programmable hardware for software defined networks. ECOC Gordon J. Brebner
2015	—	`conf`	Programmable hardware in software defined networking. OFC Gordon J. Brebner
2014	J	`jnl`	High-Speed Packet Processing using Reconfigurable Computing. IEEE Micro Gordon J. Brebner, Weirong Jiang
2014	—	`ed.`	Proceedings of the tenth ACM/IEEE symposium on Architectures for networking and communications systems, ANCS 2014, Los Angeles, CA, USA, October 20-21, 2014 ANCS Viktor K. Prasanna, Gordon J. Brebner, Isaac Keslassy
2013	J	`jnl`	ReShape: Towards a High-Level Approach to Design and Operation of Modular Reconfigurable Systems. ACM Trans. Reconfigurable Technol. Syst. Christopher E. Neely, Gordon J. Brebner, Weijia Shang
2012	B	`conf`	Optimizing packet lookup in time and space on FPGA. FPL Thilan Ganegedara, Viktor K. Prasanna, Gordon J. Brebner
2012	—	`conf`	Softly defined networking. ANCS Gordon J. Brebner
2011	—	`conf`	400 Gb/s Programmable Packet Parsing on a Single FPGA. ANCS Michael Attig, Gordon J. Brebner
2011	—	`conf`	Reconfigurable Computing for High Performance Networking Applications. ARC Gordon J. Brebner
2010	B	`conf`	Flexible and Modular Support for Timing Functions in High Performance Networking Acceleration. FPL Christopher E. Neely, Gordon J. Brebner, Weijia Shang
2010	Misc	`conf`	ShapeUp: A High-Level Design Approach to Simplify Module Interconnection on FPGAs. FCCM Christopher E. Neely, Gordon J. Brebner, Weijia Shang
2009	—	`conf`	Packets everywhere: The great opportunity for field programmable technology. FPT Gordon J. Brebner
2008	J	`jnl`	OpenDF: a dataflow toolset for reconfigurable hardware and multicore systems. SIGARCH Comput. Archit. News Shuvra S. Bhattacharyya, Gordon J. Brebner, Jörn W. Janneck, Johan Eker, Carl von Platen, Marco Mattavelli, Mickaël Raulet
2007	J	`jnl`	Editorial for the Special Issue on Field Programmable Technology. J. VLSI Signal Process. Gordon J. Brebner, Samarjit Chakraborty, Weng-Fai Wong
2006	—	`conf`	06141 Abstracts Collection -- Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures Jürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas
2006	—	`conf`	06141 Executive Summary -- Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures Jürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas
2006	A	`conf`	Building a flexible and scalable DRAM interface for networking applications on FPGAs. FPGA Jike Chong, Chidamber Kulkarni, Gordon J. Brebner
2006	—	`ed.`	Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006 Dynamically Reconfigurable Architectures Peter M. Athanas, Jürgen Becker, Gordon J. Brebner, Jürgen Teich
2006	A	`conf`	Memory centric thread synchronization on platform FPGAs. DATE Chidamber Kulkarni, Gordon J. Brebner
2006	B	`conf`	Micro-Coded Datapaths: Populating the Space Between Finite State Machine and Processor. FPL Chidamber Kulkarni, Gordon J. Brebner
2006	Misc	`conf`	Systematic Characterization of Programmable Packet Processing Pipelines. FCCM Michael Attig, Gordon J. Brebner
2005	Misc	`conf`	Mutable Codesign for Embedded Protocol Processing. FCCM Todd S. Sproull, Gordon J. Brebner, Christopher E. Neely
2005	B	`conf`	Mutable Codesign for Embedded Protocol Processing. FPL Todd S. Sproull, Gordon J. Brebner, Christopher E. Neely
2005	—	`ed.`	Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, FPT 2005, 11-14 December 2005, Singapore FPT Gordon J. Brebner, Samarjit Chakraborty, Weng-Fai Wong
2004	—	`conf`	Hyper-Programmable Architectures for Adaptable Networked Systems. ASAP Gordon J. Brebner, Philip James-Roxby, Eric Keller, Chidamber Kulkarni
2004	A*	`conf`	Mapping a domain specific language to a platform FPGA. DAC Chidamber Kulkarni, Gordon J. Brebner, Graham Schelle
2004	B	`conf`	Multithreading in a Hyper-programmable Platform for Networked Systems. FPL Philip James-Roxby, Gordon J. Brebner
2004	B	`conf`	Programmable Logic Has More Computational Power than Fixed Logic. FPL Gordon J. Brebner
2004	—	`conf`	Programming a hyper-programmable architecture for networked systems. FPT Eric Keller, Gordon J. Brebner
2004	Misc	`conf`	Time-Critical Software Deceleration in an FCCM. FCCM Philip James-Roxby, Gordon J. Brebner, Dennis Bemmann
2003	C	`conf`	Eccentric SoC Architectures as the Future Norm. DSD Gordon J. Brebner
2003	—	`conf`	Networking on chip with platform FPGAs. FPT Gordon J. Brebner, Delon Levi
2003	B	`conf`	Software Decelerators. FPL Eric Keller, Gordon J. Brebner, Philip James-Roxby
2002	B	`conf`	Multithreading for Logic-Centric Systems. FPL Gordon J. Brebner
2002	Misc	`conf`	Single-Chip Gigabit Mixed-Version IP Router on Virtex-II Pro. FCCM Gordon J. Brebner
2002	A	`conf`	Workshop Introduction. IPDPS Gordon J. Brebner
2001	B	`conf`	Chip-Based Reconfigurable Task Management. FPL Gordon J. Brebner, Oliver Diessel
2001	Misc	`conf`	Circlets: Circuitry over the Internet. FCCM Gordon J. Brebner, Irwin Kennedy
2001	B	`ed.`	Field-Programmable Logic and Applications, 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001, Proceedings FPL Gordon J. Brebner, Roger F. Woods
1999	—	`conf`	A Transactional Approach to Configuring Telecommunications Services. Databases in Telecommunications Tim Kempster, Gordon J. Brebner, Peter Thanisch
1999	B	`conf`	Reconfigurable Computing in Remote and Harsh Environments. FPL Gordon J. Brebner, Neil W. Bergmann
1998	B	`conf`	An Interactive Datasheet for the Xilinx XC6200. FPL Gordon J. Brebner
1998	Misc	`conf`	Circlets: Circuits as Applets. FCCM Gordon J. Brebner
1998	—	`conf`	ECOLE: A Configurable Environment for a Local Optical Network of Workstations. CANPC Gordon J. Brebner, Rob Pooley
1998	B	`conf`	Field-Programmable Logic: Catalyst for New Computing Paradigms. FPL Gordon J. Brebner
1998	—	`conf`	Runtime Reconfigurable Routing. IPPS/SPDP Workshops Gordon J. Brebner, Adam Donlin
1997	B	`conf`	Automatc identification of swappable logic units in XC6200 circuitry. FPL Gordon J. Brebner
1997	Misc	`conf`	The swappable logic unit: a paradigm for virtual hardware. FCCM Gordon J. Brebner
1996	B	`conf`	A Virtual Hardware Operating System for the Xilinx XC6200. FPL Gordon J. Brebner
1995	B	`conf`	Use of Reconfigurability in Variable-Length Code Detection at Video Rates. FPL Gordon J. Brebner, John Gray
1993	J	`jnl`	A CCS-based Investigation of Deadlock in a Multi-process Electronic Mail System. Formal Aspects Comput. Gordon J. Brebner
1993	J	`jnl`	Configurable array logic circuits for computing network error detection codes. J. VLSI Signal Process. Gordon J. Brebner
1981	A*	`conf`	Universal Schemes for Parallel Communication STOC Leslie G. Valiant, Gordon J. Brebner