Gordon B. Steven

24 papers C 4Journal 14Unranked 6

Year	Rank	Type	Title / Venue / Authors
2003	J	`jnl`	Two-level branch prediction using neural networks. J. Syst. Archit. Colin Egan, Gordon B. Steven, Patrick Quick, Rubén Anguera, Fleur L. Steven, Lucian N. Vintan
2002	—	`conf`	Cached Two-Level Adaptive Branch Predictors with Multiple Stages. ARCS Colin Egan, Gordon B. Steven, Lucian N. Vintan
2001	J	`jnl`	Adding static data dependence collapsing to a high-performance instruction scheduler. J. Syst. Archit. Fleur L. Steven, Colin Egan, Richard D. Potter, Gordon B. Steven
2001	C	`conf`	Applying Caching to Two-Level Adaptive Branch Prediction. DSD Colin Egan, Gordon B. Steven, Won Shim, Lucian N. Vintan
2001	C	`conf`	Dynamic Branch Prediction Using Neural Networks. DSD Gordon B. Steven, Rubén Anguera, Colin Egan, Fleur L. Steven, Lucian N. Vintan
2000	—	`conf`	Static Scheduling for Out-of-order Instruction Issue Processors. ACAC Daniel Tate, Gordon B. Steven, Fleur L. Steven
1999	C	`conf`	The impact of cache organisation on the instruction issue rate of a superscalar processor. PDP Lucian N. Vintan, Cristian Armat, Gordon B. Steven
1998	—	`conf`	The Impact of a Realistic Cache Structure on a Statically Scheduled Architecture. EUROMICRO Daniel Tate, Gordon B. Steven, Paul A. Findlay
1997	J	`jnl`	A superscalar architecture to exploit instruction level parallelism. Microprocess. Microsystems Gordon B. Steven, Bruce Christianson, Roger Collins, Richard D. Potter, Fleur L. Steven
1996	—	`conf`	Instruction Scheduling for a Superscalar Architecture. EUROMICRO Roger Collins, Gordon B. Steven
1996	—	`conf`	Investigating the Limits of Fine-Grained Parallelism in a Statically Scheduled Superscalar Architecture. Euro-Par, Vol. II Richard D. Potter, Gordon B. Steven
1995	—	`conf`	Hades-towards the design of an asynchronous superscalar processor. ASYNC C. J. Elston, D. B. Christianson, Paul A. Findlay, Gordon B. Steven
1994	J	`jnl`	An explicitly declared delayed-branch mechanism for a superscalar architecture. Microprocess. Microprogramming Roger Collins, Gordon B. Steven
1994	C	`conf`	Harp: A Statically Scheduled Multiple-instruction Issue Architecture And Its Compiler. PDP Rod Adams, Sue M. Gray, Gordon B. Steven
1993	J	`jnl`	ALU design and processor branch architecture. Microprocess. Microprogramming Gordon B. Steven, Fleur L. Steven
1993	J	`jnl`	Addressing mechanisms for VLIW and superscalar processors. Microprocess. Microprogramming Fleur L. Steven, Rod Adams, Gordon B. Steven, L. Wang, D. J. Whale
1993	J	`jnl`	Static instruction scheduling for the HARP multiple-instruction-issue architecture. Microprocess. Microsystems Sue M. Gray, Rod Adams, G. J. Green, Gordon B. Steven
1991	J	`jnl`	A parallel pipelined processor with conditional instruction execution. SIGARCH Comput. Archit. News Rod Adams, Gordon B. Steven
1990	J	`jnl`	Address and data register separation on the M68000 family. SIGARCH Comput. Archit. News Fleur L. Williams, Gordon B. Steven
1990	J	`jnl`	How useful are complex instructions? A case study using the M68000. Microprocessing and Microprogramming Fleur L. Williams, Gordon B. Steven
1990	J	`jnl`	Utilising low level parallelism in general purpose code: the HARP project. Microprocessing and Microprogramming R. G. Adams, Sue M. Gray, Gordon B. Steven
1989	J	`jnl`	HARP: A parallel pipelined RISC processor. Microprocess. Microsystems Gordon B. Steven, Sue M. Gray, R. G. Adams
1988	J	`jnl`	A novel effective address calculation mechanism for RISC microprocessors. SIGARCH Comput. Archit. News Gordon B. Steven
1988	J	`jnl`	General addressing mechanisms for microprocessors. Microprocess. Microsystems Gordon B. Steven, Fleur L. Williams