Gopalakrishnan Vijayan

26 papers A* 3A 4C 2Journal 15Unranked 2
YearRankTypeTitle / Venue / Authors
1997 — conf
Fast power loss calculation for digital static CMOS circuits.
ED&TC
Sergey Gavrilov, Alexey Glebov, Sergey G. Rusakov, David T. Blaauw, Larry G. Jones, Gopalakrishnan Vijayan
1997 A conf
Library-less synthesis for static CMOS combinational logic circuits.
ICCAD
Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David T. Blaauw
1995 C conf
PEPPER - a timing driven early floorplanner.
ICCD
Vinod Narayananan, David LaPotin, Rajesh Gupta, Gopalakrishnan Vijayan
1992 J jnl
Optimized test application timing for AC test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Vijay S. Iyengar, Gopalakrishnan Vijayan
1992 C conf
Workload-Driven Floorplanning for MIPS Optimization.
ICCD
Pradip Bose, David LaPotin, Gopalakrishnan Vijayan, Sungho Kim
1991 J jnl
A new method for floor planning using topological constraint reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Gopalakrishnan Vijayan, Ren-Song Tsay
1991 J jnl
Generalization of Min-Cut Partitioning to Tree Structures and Its Applications.
IEEE Trans. Computers
Gopalakrishnan Vijayan
1991 J jnl
On an edge ranking problem of trees and graphs.
Discret. Appl. Math.
Ananth V. Iyer, H. Donald Ratliff, Gopalakrishnan Vijayan
1991 J jnl
Planar topological routing of pad nets.
Integr.
Jan-Ming Ho, Gopalakrishnan Vijayan, C. K. Wong
1991 A conf
Test Application Timing: The Unexplored Issue in AC Test.
ITC
Vijay S. Iyengar, Gopalakrishnan Vijayan
1990 A conf
Floorplanning by Topological Constraint Reduction.
ICCAD
Gopalakrishnan Vijayan, Ren-Song Tsay
1990 J jnl
Layer assignment for multichip modules.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jan-Ming Ho, Majid Sarrafzadeh, Gopalakrishnan Vijayan, Chak-Kuen Wong
1990 J jnl
New algorithms for the rectilinear Steiner tree problem.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jan-Ming Ho, Gopalakrishnan Vijayan, Chak-Kuen Wong
1990 J jnl
Pad minimization for planar routing of multiple power nets.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jan-Ming Ho, Majid Sarrafzadeh, Gopalakrishnan Vijayan, Chak-Kuen Wong
1990 J jnl
Partitioning logic on graph structures to minimize routing cost.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Gopalakrishnan Vijayan
1989 A* conf
A New Approach to the Rectilinear Steiner Tree Problem.
DAC
Jan-Ming Ho, Gopalakrishnan Vijayan, C. K. Wong
1989 A conf
Constructing the optimal rectilinear Steiner tree derivable from a minimum spanning tree.
ICCAD
Jan-Ming Ho, Gopalakrishnan Vijayan, Chak-Kuen Wong
1989 A* conf
Min-cost Partitioning on a Tree Structure and Applications.
DAC
Gopalakrishnan Vijayan
1989 J jnl
On VHV-routing in channels with irregular boundaries.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Gopalakrishnan Vijayan, Hai Hsia Chen, Chak-Kuen Wong
1988 J jnl
Optimal Node Ranking of Trees.
Inf. Process. Lett.
Ananth V. Iyer, H. Donald Ratliff, Gopalakrishnan Vijayan
1987 J jnl
An improved edge bound on the interval number of a graph.
J. Graph Theory
Jeremy P. Spinrad, Gopalakrishnan Vijayan, Douglas B. West
1986 — conf
Geometry of Planar Graphs with Angles.
SCG
Gopalakrishnan Vijayan
1985 J jnl
Rectilinear Graphs and their Embeddings.
SIAM J. Comput.
Gopalakrishnan Vijayan, Avi Wigderson
1985 J jnl
Worst case analysis of a graph coloring algorithm.
Discret. Appl. Math.
Jeremy P. Spinrad, Gopalakrishnan Vijayan
1983 J jnl
VLSI Layout as Programming.
ACM Trans. Program. Lang. Syst.
Richard J. Lipton, Jacobo Valdes, Gopalakrishnan Vijayan, Stephen C. North, Robert Sedgewick
1982 A* conf
ALI: A procedural language to describe VLSI layouts.
DAC
Richard J. Lipton, Stephen C. North, Robert Sedgewick, Jacobo Valdes, Gopalakrishnan Vijayan