Gopalakrishnan Lakshminarayanan

28 papers Misc 1Journal 23Unranked 4

Year	Rank	Type	Title / Venue / Authors
2023	J	`jnl`	Framework for QCA Layout Generation and Rules for Rotated Cell Design. J. Circuits Syst. Comput. Raja Sekar Kumaresan, Marshal Raj, Gopalakrishnan Lakshminarayanan
2023	J	`jnl`	SaHNoC: an optimal energy efficient hybrid networks-on-chip architecture. J. Supercomput. Aravindhan Alagarsamy, Sundarakannan Mahilmaran, Gopalakrishnan Lakshminarayanan, Seok-Bum Ko
2022	J	`jnl`	An Efficient Lossless Telemetry Data Compression and Fault Analysis System Using 2SMLZ and CMOW-DLNN. Wirel. Pers. Commun. Parameshwaran Ramalingam, R. Thanuja, R. Bhavani, Gopalakrishnan Lakshminarayanan
2022	J	`jnl`	FRDS: An efficient unique on-Chip interconnection network architecture. Integr. Aravindhan Alagarsamy, Sundarakannan Mahilmaran, Gopalakrishnan Lakshminarayanan, Seok-Bum Ko
2022	J	`jnl`	SMA: A constructive partitioning based mapping approach for Networks-on-Chip. Microprocess. Microsystems Aravindhan Alagarsamy, Sundarakannan Mahilmaran, Gopalakrishnan Lakshminarayanan, Seok-Bum Ko
2021	J	`jnl`	A Real-Time Architecture for Pruning the Effectual Computations in Deep Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. Mohammadreza Asadikouhanjani, Hao Zhang, Gopalakrishnan Lakshminarayanan, Hyuk-Jae Lee, Seok-Bum Ko
2021	J	`jnl`	A low latency modular-level deeply integrated MFCC feature extraction architecture for speech recognition. Integr. Bibin Sam Paul S, Antony Xavier Glittas, Gopalakrishnan Lakshminarayanan
2021	J	`jnl`	A novel boundary elemental analysis based frequency domain adaptive sampling technique for aerospace application. Microprocess. Microsystems R. Umamaheswaran, Parameshwaran Ramalingam, Marshal Raj, Gopalakrishnan Lakshminarayanan, S. Thiruppathirajan
2021	J	`jnl`	Kinematic adaptive frequency sampling combined spatio temporal features for snow monitoring in aerospace applications. Expert Syst. Appl. Parameshwaran Ramalingam, Gopalakrishnan Lakshminarayanan, Manikandan Ramachandran, Rizwan Patan
2021	J	`jnl`	Reliable SRAM using NAND-NOR Gate in beyond-CMOS QCA technology. IET Comput. Digit. Tech. Marshal Raj, Gopalakrishnan Lakshminarayanan, Seok-Bum Ko
2020	—	`conf`	Area-Efficient D-Flip Flop and XOR in QCA. ICCCNT Raja Sekar Kumaresan, Marshal Raj, Gopalakrishnan Lakshminarayanan
2020	J	`jnl`	Configurable Logic Blocks and Memory Blocks for Beyond-CMOS FPGA-Based Embedded Systems. IEEE Embed. Syst. Lett. Marshal Raj, Gopalakrishnan Lakshminarayanan, Seok-Bum Ko, Nagi Naganathan, N. Ramasubramanian
2019	J	`jnl`	A Self-Adaptive Mapping Approach for Network on Chip With Low Power Consumption. IEEE Access Aravindhan Alagarsamy, Gopalakrishnan Lakshminarayanan, Sundarakannan Mahilmaran, Seok-Bum Ko
2019	—	`conf`	High Speed Controllable Inverter for Adder-Subtractor in QCA. ICCCNT Marshal Raj, Raja Sekar Kumaresan, Gopalakrishnan Lakshminarayanan
2019	J	`jnl`	KBMA: A knowledge-based multi-objective application mapping approach for 3D NoC. IET Comput. Digit. Tech. Aravindhan Alagarsamy, Gopalakrishnan Lakshminarayanan, Seok-Bum Ko
2019	J	`jnl`	Low-complex processing element architecture for successive cancellation decoder. Integr. Geethu Sathees Babu, Lakshmi Renuka Madala, Gopalakrishnan Lakshminarayanan, Mathini Sellathurai
2019	—	`conf`	Optimized Multiplexer and Exor gate in 4-dot 2-electron QCA using Novel Input Technique. ICCCNT Marshal Raj, Raja Sekar Kumaresan, Gopalakrishnan Lakshminarayanan
2019	J	`jnl`	Reconfigurable address generator for multi-standard interleaver. Microprocess. Microsystems Geethu Sathees Babu, Gopalakrishnan Lakshminarayanan
2016	J	`jnl`	A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO. IEEE Trans. Very Large Scale Integr. Syst. Antony Xavier Glittas, Mathini Sellathurai, Gopalakrishnan Lakshminarayanan
2016	J	`jnl`	Low complexity and area efficient reconfigurable multimode interleaver address generator for multistandard radios. IET Comput. Digit. Tech. Nithish Kumar Venkatachalam, Gopalakrishnan Lakshminarayanan, Mathini Sellathurai
2016	J	`jnl`	Two-parallel pipelined fast Fourier transform processors for real-valued signals. IET Circuits Devices Syst. Antony Xavier Glittas, Mathini Sellathurai, Gopalakrishnan Lakshminarayanan
2015	J	`jnl`	An Improved Reconfigurable Finite Impulse Response Filter Using Common Subexpression Elimination Algorithm for Cognitive Radio. J. Low Power Electron. Venkatachalam Nithish Kumar, Koteswara Rao Nalluri, Gopalakrishnan Lakshminarayanan, Mathini Sellathurai
2014	J	`jnl`	Low Power and Area Efficient Carry Select Adder. J. Low Power Electron. Venkatachalam Nithish Kumar, Pani Prithvi Raj, Gopalakrishnan Lakshminarayanan, Mathini Sellathurai
2014	—	`conf`	Pipelined FFT architectures for real-time signal processing and wireless communication applications. VDAT Antony Xavier Glittas, Gopalakrishnan Lakshminarayanan
2012	Misc	`conf`	A Novel Encoding Scheme for Low Power in Network on Chip Links. VLSI Design Deepa N. Sarma, Gopalakrishnan Lakshminarayanan, K. V. R. Suryakiran Chavali
2008	J	`jnl`	Automation techniques for implementation of hybrid wave-pipelined 2D DWT. J. Real Time Image Process. G. Seetharaman, B. Venkataramani, Gopalakrishnan Lakshminarayanan
2008	J	`jnl`	VLSI Implementation of Hybrid Wave-Pipelined 2D DWT Using Lifting Scheme. VLSI Design Gopalakrishnan Seetharaman, Balasubramanian Venkataramani, Gopalakrishnan Lakshminarayanan
2005	J	`jnl`	Optimization Techniques for FPGA-Based Wave-Pipelined DSP Blocks. IEEE Trans. Very Large Scale Integr. Syst. Gopalakrishnan Lakshminarayanan, B. Venkataramani