Gong Chen

12 papers C 2Journal 4Unranked 6
YearRankTypeTitle / Venue / Authors
2018 J jnl
Routable and Matched Layout Styles for Analog Module Generation.
ACM Trans. Design Autom. Electr. Syst.
Bo Liu, Gong Chen, Bo Yang, Shigetoshi Nakatake
2016 — conf
A multi-functional memory unit with PLA-based reconfigurable decoder.
ReConFig
Nobuyuki Yahiro, Bo Liu, Atsushi Nanri, Shigetoshi Nakatake, Yasuhiro Takashima, Gong Chen
2016 J jnl
DC Characteristics and Variability on 90nm CMOS Transistor Array-Style Analog Layout.
ACM Trans. Design Autom. Electr. Syst.
Gong Chen, Toru Fujimura, Qing Dong, Shigetoshi Nakatake, Bo Yang
2016 — conf
Routability of twisted common-centroid capacitor array under signal coupling constraints.
MWSCAS
Gong Chen, Bo Liu, Shigetoshi Nakatake, Bo Yang
2016 — conf
Twin-row-style for MOS analog layout.
ICECS
Bo Liu, Shigetoshi Nakatake, Bo Yang, Gong Chen
2015 J jnl
Layout Dependent Effect-Aware Leakage Current Reduction and Its Application to Low-Power SAR-ADC.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Gong Chen, Yu Zhang, Qing Dong, Mingyu Li, Shigetoshi Nakatake
2013 — conf
A 9-bit 50msps SAR ADC with pre-charge VCM -based double input range algorithm.
ACM Great Lakes Symposium on VLSI
Gong Chen, Bo Yang, Yu Zhang, Qing Dong, Shigetoshi Nakatake
2013 — conf
A comparator energy model considering shallow trench isolation stress by geometric programming.
ISQED
Gong Chen, Yu Zhang, Bo Yang, Qing Dong, Shigetoshi Nakatake
2013 J jnl
Analog Circuit Synthesis with Constraint Generation of Layout-Dependent Effects by Geometric Programming.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yu Zhang, Gong Chen, Bo Yang, Jing Li, Qing Dong, Mingyu Li, Shigetoshi Nakatake
2013 C conf
Performance-driven SRAM macro design with parameterized cell considering layout-dependent effects.
VLSI-SoC
Yu Zhang, Gong Chen, Qing Dong, Mingyu Li, Shigetoshi Nakatake
2012 C conf
A retargeting methodology of nano-watt CMOS reference circuit based on advanced compact MOSFET model.
ISCAS
Gong Chen, Bo Yang, Shigetoshi Nakatake, Zhangcai Huang, Yasuaki Inoue
2012 — conf
Transistor channel decomposition for structured analog layout, manufacturability and low-power applications.
ISQED
Qing Dong, Bo Yang, Gong Chen, Jing Li, Shigetoshi Nakatake