Giuseppe Tagliavini

91 papers A* 2A 12C 4Misc 1Journal 41Unranked 30

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	OpenBioNER-v2: A suite of lightweight models for zero-shot medical named entity recognition via type descriptions. Expert Syst. Appl. Alessio Cocchieri, Giacomo Frisoni, Francesco Zangrillo, Luca Ragazzi, Marcos Martínez Galindo, Giuseppe Tagliavini, Gianluca Moro
2026	—	`conf`	ReMedQA: Are We Done With Medical Multiple-Choice Benchmarks? EACL (Volume 1: Long Papers) Alessio Cocchieri, Luca Ragazzi, Giuseppe Tagliavini, Gianluca Moro
2025	—	`conf`	"What do you call a dog that is incontrovertibly true? Dogma": Testing LLM Generalization through Humor. ACL (1) Alessio Cocchieri, Luca Ragazzi, Paolo Italiani, Giuseppe Tagliavini, Gianluca Moro
2025	A*	`conf`	Can Large Language Models Win the International Mathematical Games? EMNLP Alessio Cocchieri, Luca Ragazzi, Giuseppe Tagliavini, Lorenzo Tordi, Antonella Carbonaro, Gianluca Moro
2025	—	`conf`	Enabling Real-Time Streaming Temporal Convolution Network Inference on Ultra-Low-Power Microcontrollers. ISVLSI Seyed Ahmad Mirsalari, Marco Fariselli, Léo Bijar, Francesco Paci, Luca Benini, Giuseppe Tagliavini
2025	J	`jnl`	Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing. CoRR Mattia Sinigaglia, Amirhossein Kiamarzi, Marco Bertuletti, Luigi Ghionda, Mattia Orlandi, Riccardo Tedeschi, Aurora Di Giampietro, Yvan Tortorella, Luca Bertaccini, Simone Benatti, Giuseppe Tagliavini, Luca Benini, Francesco Conti, Davide Rossi
2025	J	`jnl`	Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing. IEEE Trans. Circuits Syst. I Regul. Pap. Mattia Sinigaglia, Amirhossein Kiamarzi, Marco Bertuletti, Luigi Ghionda, Mattia Orlandi, Riccardo Tedeschi, Aurora Di Giampietro, Yvan Tortorella, Luca Bertaccini, Simone Benatti, Giuseppe Tagliavini, Luca Benini, Francesco Conti, Davide Rossi
2025	A	`conf`	Multi-Partner Project: Advancing the EDA Tools Landscape for the European RISC-V Ecosystem in TRISTAN. DATE Fatma Jebali, Caaliph Andriamisaina, Mathieu Jan, Wolfgang Ecker, Florian Egert, Bernhard Fischer, Alessio Burrello, Daniele Jahier Pagliari, Sara Vinco, Giuseppe Tagliavini, Ingo Feldner, Andreas Mauderer, Axel Sauer, Arnór Kristmundsson, Alexander Schober, Téo Bernier, Matti Käyrä, Ulf Schlichtmann, Rocco Jonack
2025	—	`conf`	OpenBioNER: Lightweight Open-Domain Biomedical Named Entity Recognition Through Entity Type Description. NAACL (Findings) Alessio Cocchieri, Giacomo Frisoni, Marcos Martínez Galindo, Gianluca Moro, Giuseppe Tagliavini, Francesco Candoli
2025	J	`jnl`	Parallelization is All System Identification Needs: End-to-End Vibration Diagnostics on a Multicore RISC-V Edge Device. IEEE Internet Things J. Amirhossein Kiamarzi, Amirhossein Moallemi, Federica Zonzini, Davide Brunelli, Davide Rossi, Giuseppe Tagliavini
2025	J	`jnl`	Synergistic Memory Optimisations: Precision Tuning in Heterogeneous Memory Hierarchies. IEEE Trans. Computers Gabriele Magnani, Daniele Cattaneo, Lev Denisov, Giuseppe Tagliavini, Giovanni Agosta, Stefano Cherubin
2025	—	`conf`	ZeroNER: Fueling Zero-Shot Named Entity Recognition via Entity Type Descriptions. ACL (Findings) Alessio Cocchieri, Marcos Martínez Galindo, Giacomo Frisoni, Gianluca Moro, Claudio Sartori, Giuseppe Tagliavini
2024	—	`conf`	Balancing Accuracy and Energy Efficiency on Ultra-Law-Power Platforms for ECG Analysis. COINS Benedetta Mazzoni, Luca Bompani, Mattia Orlandi, Simone Benatti, Giuseppe Tagliavini
2024	J	`jnl`	Open-Source Heterogeneous SoCs for AI: The PULP Platform Experience. CoRR Francesco Conti, Angelo Garofalo, Davide Rossi, Giuseppe Tagliavini, Luca Benini
2024	—	`conf`	QR-PULP: Streamlining QR Decomposition for RISC-V Parallel Ultra-Low-Power Platforms. CF Amirhossein Kiamarzi, Davide Rossi, Giuseppe Tagliavini
2024	—	`conf`	SeTHet - Sending Tuned numbers over DMA onto Heterogeneous clusters: an automated precision tuning story. CF Gabriele Magnani, Daniele Cattaneo, Lev Denisov, Giuseppe Tagliavini, Giovanni Agosta, Stefano Cherubin
2023	—	`conf`	ANGELS - Smart Steering Wheel for Driver Safety. IWASI Andrea Amidei, Pierangelo Maria Rapa, Giuseppe Tagliavini, Roberto Rabbeni, Paolo Pavan, Simone Benatti
2023	J	`jnl`	DNN Is Not All You Need: Parallelizing Non-neural ML Algorithms on Ultra-low-power IoT Processors. ACM Trans. Embed. Comput. Syst. Enrico Tabanelli, Giuseppe Tagliavini, Luca Benini
2023	J	`jnl`	Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode. IEEE Trans. Circuits Syst. I Regul. Pap. Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Alfio Di Mauro, Luca Benini, Davide Rossi
2023	A	`conf`	End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture. DATE Nazareno Bruschi, Giuseppe Tagliavini, Angelo Garofalo, Francesco Conti, Irem Boybat, Luca Benini, Davide Rossi
2023	A	`conf`	HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC. DATE Luca Valente, Yvan Tortorella, Mattia Sinigaglia, Giuseppe Tagliavini, Alessandro Capotondi, Luca Benini, Davide Rossi
2023	—	`conf`	Optimizing Self-Organizing Maps for Bacterial Genome Identification on Parallel Ultra-Low-Power Platforms. ICECS Seyed Ahmad Mirsalari, Saba Yousefzadeh, Giuseppe Tagliavini, Dimitrios Stathis, Ahmed Hemani
2023	—	`conf`	RUST-Encoded Stream Ciphers on a RISC-V Parallel Ultra-Low-Power Processor (Invited Paper). PARMA-DITAM Francesco Barchi, Giacomo Pasini, Emanuele Parisi, Giuseppe Tagliavini, Andrea Bartolini, Andrea Acquaviva
2023	J	`jnl`	Scalable Hierarchical Instruction Cache for Ultra-Low-Power Processors Clusters. CoRR Jie Chen, Igor Loi, Eric Flamand, Giuseppe Tagliavini, Luca Benini, Davide Rossi
2023	J	`jnl`	Scalable Hierarchical Instruction Cache for Ultralow-Power Processors Clusters. IEEE Trans. Very Large Scale Integr. Syst. Jie Chen, Igor Loi, Eric Flamand, Giuseppe Tagliavini, Luca Benini, Davide Rossi
2023	A	`conf`	TransLib: A Library to Explore Transprecision Floating-Point Arithmetic on Multi-Core IoT End-Nodes. DATE Seyed Ahmad Mirsalari, Giuseppe Tagliavini, Davide Rossi, Luca Benini
2022	J	`jnl`	A Low-Power Transprecision Floating-Point Cluster for Efficient Near-Sensor Data Analytics. IEEE Trans. Parallel Distributed Syst. Fabio Montagna, Stefan Mach, Simone Benatti, Angelo Garofalo, Gianmarco Ottavi, Luca Benini, Davide Rossi, Giuseppe Tagliavini
2022	—	`conf`	An Optimized Heart Rate Detection System Based on Low-Power Microcontroller Platforms for Biosignal Processing. SYSINT Benedetta Mazzoni, Giuseppe Tagliavini, Luca Benini, Simone Benatti
2022	J	`jnl`	Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode. CoRR Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Alfio Di Mauro, Luca Benini, Davide Rossi
2022	J	`jnl`	End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture. CoRR Nazareno Bruschi, Giuseppe Tagliavini, Angelo Garofalo, Francesco Conti, Irem Boybat, Luca Benini, Davide Rossi
2022	J	`jnl`	GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors. CoRR Nazareno Bruschi, Germain Haugou, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
2022	J	`jnl`	HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC. CoRR Luca Valente, Yvan Tortorella, Mattia Sinigaglia, Giuseppe Tagliavini, Alessandro Capotondi, Luca Benini, Davide Rossi
2022	J	`jnl`	Optimizing Random Forest-Based Inference on RISC-V MCUs at the Extreme Edge. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Enrico Tabanelli, Giuseppe Tagliavini, Luca Benini
2022	—	`conf`	PULP-TrainLib: Enabling On-Device Training for RISC-V Multi-core MCUs Through Performance-Driven Autotuning. SAMOS Davide Nadalini, Manuele Rusci, Giuseppe Tagliavini, Leonardo Ravaglia, Luca Benini, Francesco Conti
2022	—	`conf`	Scale up your In-Memory Accelerator: Leveraging Wireless-on-Chip Communication for AIMC-based CNN Inference. AICAS Nazareno Bruschi, Giuseppe Tagliavini, Francesco Conti, Sergi Abadal, Albert Cabellos-Aparicio, Eduard Alarcón, Geethan Karunaratne, Irem Boybat, Luca Benini, Davide Rossi
2022	J	`jnl`	Scale up your In-Memory Accelerator: Leveraging Wireless-on-Chip Communication for AIMC-based CNN Inference. CoRR Nazareno Bruschi, Giuseppe Tagliavini, Francesco Conti, Sergi Abadal, Albert Cabellos-Aparicio, Eduard Alarcón, Geethan Karunaratne, Irem Boybat, Luca Benini, Davide Rossi
2022	J	`jnl`	Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. IEEE J. Solid State Circuits Davide Rossi, Francesco Conti, Manuel Eggimann, Alfio Di Mauro, Giuseppe Tagliavini, Stefan Mach, Marco Guermandi, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini
2021	—	`conf`	4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. ISSCC Davide Rossi, Francesco Conti, Manuel Eggimann, Stefan Mach, Alfio Di Mauro, Marco Guermandi, Giuseppe Tagliavini, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini
2021	—	`conf`	A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode. ESSCIRC Angelo Garofalo, Gianmarco Ottavi, Alfio Di Mauro, Francesco Conti, Giuseppe Tagliavini, Luca Benini, Davide Rossi
2021	J	`jnl`	DNN is not all you need: Parallelizing Non-Neural ML Algorithms on Ultra-Low-Power IoT Processors. CoRR Enrico Tabanelli, Giuseppe Tagliavini, Luca Benini
2021	J	`jnl`	DORY: Automatic End-to-End Deployment of Real-World DNNs on Low-Cost IoT MCUs. IEEE Trans. Computers Alessio Burrello, Angelo Garofalo, Nazareno Bruschi, Giuseppe Tagliavini, Davide Rossi, Francesco Conti
2021	J	`jnl`	Efficient Transform Algorithms for Parallel Ultra-Low-Power IoT End Nodes. IEEE Embed. Syst. Lett. Benedetta Mazzoni, Simone Benatti, Luca Benini, Giuseppe Tagliavini
2021	J	`jnl`	Energy-Efficient Hardware-Accelerated Synchronization for Shared-L1-Memory Multiprocessor Clusters. IEEE Trans. Parallel Distributed Syst. Florian Glaser, Giuseppe Tagliavini, Davide Rossi, Germain Haugou, Qiuting Huang, Luca Benini
2021	C	`conf`	GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors. ICCD Nazareno Bruschi, Germain Haugou, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
2021	—	`conf`	RVfplib: A Fast and Compact Open-Source Floating-Point Emulation Library for Tiny RISC-V Processors. SAMOS Matteo Perotti, Giuseppe Tagliavini, Stefan Mach, Luca Bertaccini, Luca Benini
2021	A	`conf`	Source Code Classification for Energy Efficiency in Parallel Ultra Low-Power Microcontrollers. DATE Emanuele Parisi, Francesco Barchi, Andrea Bartolini, Giuseppe Tagliavini, Andrea Acquaviva
2021	—	`conf`	Streamlining the OpenMP Programming Model on Ultra-Low-Power Multi-core MCUs. ARCS Fabio Montagna, Giuseppe Tagliavini, Davide Rossi, Angelo Garofalo, Luca Benini
2021	—	`conf`	Towards Long-term Non-invasive Monitoring for Epilepsy via Wearable EEG Devices. BioCAS Thorir Mar Ingolfsson, Andrea Cossettini, Xiaying Wang, Enrico Tabanelli, Giuseppe Tagliavini, Philippe Ryvlin, Luca Benini, Simone Benatti
2021	J	`jnl`	Towards Long-term Non-invasive Monitoring for Epilepsy via Wearable EEG Devices. CoRR Thorir Mar Ingolfsson, Andrea Cossettini, Xiaying Wang, Enrico Tabanelli, Giuseppe Tagliavini, Philippe Ryvlin, Luca Benini, Simone Benatti
2021	J	`jnl`	Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. CoRR Davide Rossi, Francesco Conti, Manuel Eggimann, Alfio Di Mauro, Giuseppe Tagliavini, Stefan Mach, Marco Guermandi, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini
2021	J	`jnl`	XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V Based IoT End Nodes. IEEE Trans. Emerg. Top. Comput. Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
2021	C	`conf`	XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V based IoT End Nodes. ARITH Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
2020	—	`conf`	A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference. ISVLSI Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
2020	J	`jnl`	A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference. CoRR Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
2020	J	`jnl`	A transprecision floating-point cluster for efficient near-sensor data analytics. CoRR Fabio Montagna, Stefan Mach, Simone Benatti, Angelo Garofalo, Gianmarco Ottavi, Luca Benini, Davide Rossi, Giuseppe Tagliavini
2020	J	`jnl`	Combining Learning and Optimization for Transprecision Computing. CoRR Andrea Borghesi, Giuseppe Tagliavini, Michele Lombardi, Luca Benini, Michela Milano
2020	—	`conf`	Combining learning and optimization for transprecision computing. CF Andrea Borghesi, Giuseppe Tagliavini, Michele Lombardi, Luca Benini, Michela Milano
2020	J	`jnl`	DORY: Automatic End-to-End Deployment of Real-World DNNs on Low-Cost IoT MCUs. CoRR Alessio Burrello, Angelo Garofalo, Nazareno Bruschi, Giuseppe Tagliavini, Davide Rossi, Francesco Conti
2020	J	`jnl`	Enabling Mixed-Precision Quantized Neural Networks in Extreme-Edge Devices. CoRR Nazareno Bruschi, Angelo Garofalo, Francesco Conti, Giuseppe Tagliavini, Davide Rossi
2020	—	`conf`	Enabling mixed-precision quantized neural networks in extreme-edge devices. CF Nazareno Bruschi, Angelo Garofalo, Francesco Conti, Giuseppe Tagliavini, Davide Rossi
2020	J	`jnl`	Energy-Efficient Hardware-Accelerated Synchronization for Shared-L1-Memory Multiprocessor Clusters. CoRR Florian Glaser, Giuseppe Tagliavini, Davide Rossi, Germain Haugou, Qiuting Huang, Luca Benini
2020	J	`jnl`	FlexFloat: A Software Library for Transprecision Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Giuseppe Tagliavini, Andrea Marongiu, Luca Benini
2020	J	`jnl`	Source Code Classification for Energy Efficiency in Parallel Ultra Low-Power Microcontrollers. CoRR Emanuele Parisi, Francesco Barchi, Andrea Bartolini, Giuseppe Tagliavini, Andrea Acquaviva
2020	A	`conf`	TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE. DATE Rohit Prasad, Satyajit Das, Kevin J. M. Martin, Giuseppe Tagliavini, Philippe Coussy, Luca Benini, Davide Rossi
2020	A	`conf`	XpulpNN: Accelerating Quantized Neural Networks on RISC-V Processors Through ISA Extensions. DATE Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Davide Rossi, Luca Benini
2020	J	`jnl`	XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Network on RISC-V based IoT End Nodes. CoRR Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
2019	J	`jnl`	BioWolf: A Sub-10-mW 8-Channel Advanced Brain-Computer Interface Platform With a Nine-Core Processor and BLE Connectivity. IEEE Trans. Biomed. Circuits Syst. Victor Javier Kartsch, Giuseppe Tagliavini, Marco Guermandi, Simone Benatti, Davide Rossi, Luca Benini
2019	A	`conf`	Design and Evaluation of SmallFloat SIMD extensions to the RISC-V ISA. DATE Giuseppe Tagliavini, Stefan Mach, Davide Rossi, Andrea Marongiu, Luca Benini
2019	J	`jnl`	Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing. IEEE J. Solid State Circuits Antonio Pullini, Davide Rossi, Igor Loi, Giuseppe Tagliavini, Luca Benini
2018	C	`conf`	A Transprecision Floating-Point Architecture for Energy-Efficient Embedded Computing. ISCAS Stefan Mach, Davide Rossi, Giuseppe Tagliavini, Andrea Marongiu, Luca Benini
2018	A	`conf`	A transprecision floating-point platform for ultra-low power computing. DATE Giuseppe Tagliavini, Stefan Mach, Davide Rossi, Andrea Marongiu, Luca Benini
2018	J	`jnl`	Optimizing memory bandwidth exploitation for OpenVX applications on embedded many-core accelerators. J. Real Time Image Process. Giuseppe Tagliavini, Germain Haugou, Andrea Marongiu, Luca Benini
2018	J	`jnl`	Synergistic HW/SW Approximation Techniques for Ultralow-Power Parallel Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Giuseppe Tagliavini, Davide Rossi, Andrea Marongiu, Luca Benini
2018	A	`conf`	The transprecision computing paradigm: Concept, design, and applications. DATE A. Cristiano I. Malossi, Michael Schaffner, Anca Molnos, Luca Gammaitoni, Giuseppe Tagliavini, Andrew P. J. Emerson, Andrés Tomás, Dimitrios S. Nikolopoulos, Eric Flamand, Norbert Wehn
2018	J	`jnl`	Unleashing Fine-Grained Parallelism on Embedded Many-Core Accelerators with Lightweight OpenMP Tasking. IEEE Trans. Parallel Distributed Syst. Giuseppe Tagliavini, Daniele Cesarini, Andrea Marongiu
2017	J	`jnl`	A Transprecision Floating-Point Platform for Ultra-Low Power Computing. CoRR Giuseppe Tagliavini, Stefan Mach, Davide Rossi, Andrea Marongiu, Luca Benini
2017	—	`—`	Optimization Techniques for Parallel Programming of Embedded Many-Core Computing Platforms. Giuseppe Tagliavini
2016	—	`conf`	Always-on motion detection with application-level error control on a near-threshold approximate computing platform. ICECS Giuseppe Tagliavini, Andrea Marongiu, Davide Rossi, Luca Benini
2016	Misc	`conf`	Enabling OpenVX support in mW-scale parallel accelerators. CASES Giuseppe Tagliavini, Germain Haugou, Andrea Marongiu, Luca Benini
2015	C	`conf`	A framework for optimizing OpenVX applications performance on embedded manycore accelerators. SCOPES Giuseppe Tagliavini, Germain Haugou, Andrea Marongiu, Luca Benini
2015	—	`conf`	ADRENALINE: An OpenVX Environment to Optimize Embedded Vision Applications on Many-core Accelerators. MCSoC Giuseppe Tagliavini, Germain Haugou, Andrea Marongiu, Luca Benini
2015	A*	`conf`	Exploring architectural heterogeneity in intelligent vision systems. HPCA Nandhini Chandramoorthy, Giuseppe Tagliavini, Kevin M. Irick, Antonio Pullini, Siddharth Advani, Sulaiman Al Habsi, Matthew Cotter, John Sampson, Vijaykrishnan Narayanan, Luca Benini
2015	—	`conf`	PULP: A parallel ultra low power platform for next generation IoT applications. Hot Chips Symposium Davide Rossi, Francesco Conti, Andrea Marongiu, Antonio Pullini, Igor Loi, Michael Gautschi, Giuseppe Tagliavini, Alessandro Capotondi, Philippe Flatresse, Luca Benini
2015	J	`jnl`	Simplifying Many-Core-Based Heterogeneous SoC Programming With Offload Directives. IEEE Trans. Ind. Informatics Andrea Marongiu, Alessandro Capotondi, Giuseppe Tagliavini, Luca Benini
2015	—	`conf`	Synergistic Architecture and Programming Model Support for Approximate Micropower Computing. ISVLSI Giuseppe Tagliavini, Davide Rossi, Luca Benini, Andrea Marongiu
2014	—	`conf`	Optimizing memory bandwidth in OpenVX graph execution on embedded many-core accelerators. DASIP Giuseppe Tagliavini, Germain Haugou, Luca Benini
2014	—	`conf`	Supporting localized OpenVX kernel execution for efficient computer vision application development on STHORM many-core platform. Conf. Computing Frontiers Giuseppe Tagliavini, Germain Haugou, Luca Benini
2014	A	`conf`	Tightly-coupled hardware support to dynamic parallelism acceleration in embedded shared memory clusters. DATE Paolo Burgio, Giuseppe Tagliavini, Francesco Conti, Andrea Marongiu, Luca Benini
2013	A	`conf`	Enabling fine-grained OpenMP tasking on tightly-coupled shared memory clusters. DATE Paolo Burgio, Giuseppe Tagliavini, Andrea Marongiu, Luca Benini
2013	—	`conf`	Improving the programmability of STHORM-based heterogeneous systems with offload-enabled OpenMP. MES Andrea Marongiu, Alessandro Capotondi, Giuseppe Tagliavini, Luca Benini
2011	—	`conf`	MPOpt-Cell: a high-performance data-flow programming environment for the CELL BE processor. Conf. Computing Frontiers Alessio Franceschelli, Paolo Burgio, Giuseppe Tagliavini, Andrea Marongiu, Martino Ruggiero, Michele Lombardi, Alessio Bonfietti, Michela Milano, Luca Benini