Giuseppe Natale

14 papers A 2B 1C 1Journal 4Unranked 5
YearRankTypeTitle / Venue / Authors
2024 J jnl
On the Computation of 2-Dimensional Recurrence Equations.
CoRR
Giuseppe Natale
2021 J jnl
Enhancing the Scalability of Multi-FPGA Stencil Computations via Highly Optimized HDL Components.
ACM Trans. Reconfigurable Technol. Syst.
Enrico Reggiani, Emanuele Del Sozzo, Davide Conficconi, Giuseppe Natale, Carlo Moroni, Marco D. Santambrogio
2020 J jnl
Enabling transparent hardware acceleration on Zynq SoC for scientific computing.
SIGBED Rev.
Luca Stornaiuolo, Filippo Carloni, Riccardo Pressiani, Giuseppe Natale, Marco D. Santambrogio, Donatella Sciuto
2019 — —
On how to design optimized spatial architectures: from iterative stencils to convolutional neural networks.
Giuseppe Natale
2018 — conf
A Framework with Cloud Integration for CNN Acceleration on FPGA Devices.
IPDPS Workshops
Niccolo Raspa, Giuseppe Natale, Marco Bacis, Marco D. Santambrogio
2018 — conf
An FPGA-Based Acceleration Methodology and Performance Model for Iterative Stencils.
IPDPS Workshops
Enrico Reggiani, Giuseppe Natale, Carlo Moroni, Marco D. Santambrogio
2017 — conf
A CAD Open Platform for High Performance Reconfigurable Systems in the EXTRA Project.
ISVLSI
Marco Rabozzi, Rolando Brondolin, Giuseppe Natale, Emanuele Del Sozzo, Michael Hübner, Andreas Brokalakis, Catalin Bogdan Ciobanu, Dirk Stroobandt, Marco Domenico Santambrogio
2017 C conf
A Feedback-Based Design Space Exploration Subsystem for the Automation of Architectures Synthesis on Proprietary FPGA Toolchains.
DSD
Alessandro Pappalardo, Giuseppe Natale, Marco Domenico Santambrogio
2017 — conf
A Pipelined and Scalable Dataflow Implementation of Convolutional Neural Networks on FPGA.
IPDPS Workshops
Marco Bacis, Giuseppe Natale, Emanuele Del Sozzo, Marco Domenico Santambrogio
2017 A conf
Heterogeneous exascale supercomputing: The role of CAD in the exaFPGA project.
DATE
Marco Rabozzi, Giuseppe Natale, Emanuele Del Sozzo, Alberto Scolari, Luca Stornaiuolo, Marco D. Santambrogio
2017 — conf
On How to Design Dataflow FPGA-Based Accelerators for Convolutional Neural Networks.
ISVLSI
Giuseppe Natale, Marco Bacis, Marco Domenico Santambrogio
2017 B conf
Optimizing streaming stencil time-step designs via FPGA floorplanning.
FPL
Marco Rabozzi, Giuseppe Natale, Biagio Festa, Antonio Miele, Marco D. Santambrogio
2016 A conf
A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops.
ICCAD
Giuseppe Natale, Giulio Stramondo, Pietro Bressana, Riccardo Cattaneo, Donatella Sciuto, Marco D. Santambrogio
2016 J jnl
On How to Accelerate Iterative Stencil Loops: A Scalable Streaming-Based Approach.
ACM Trans. Archit. Code Optim.
Riccardo Cattaneo, Giuseppe Natale, Carlo Sicignano, Donatella Sciuto, Marco Domenico Santambrogio