Giuseppe Ascia

96 papers A* 3A 4B 7C 9Misc 6Journal 35Unranked 32
YearRankTypeTitle / Venue / Authors
2026 J jnl
Assessing the Role of Communication in Modular Multi-Core Quantum Systems.
ACM Trans. Design Autom. Electr. Syst.
Maurizio Palesi, Enrico Russo, Giuseppe Ascia, Hamaad Rafique, Davide Patti, Vincenzo Catania, Sergi Abadal, Abhijit Das, Pau Escofet, Eduard Alarcón, Carmen G. Almudéver
2026 J jnl
CHAOS: Controlled Hardware fAult injectOr System for gem5.
CoRR
Elio Vinciguerra, Enrico Russo, Giuseppe Ascia, Maurizio Palesi
2025 J jnl
A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms.
ACM Comput. Surv.
Cristina Silvano, Daniele Ielmini, Fabrizio Ferrandi, Leandro Fiorin, Serena Curzel, Luca Benini, Francesco Conti, Angelo Garofalo, Cristian Zambelli, Enrico Calore, Sebastiano Fabio Schifano, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Nicola Petra, Davide De Caro, Luciano Lavagno, Teodoro Urso, Valeria Cardellini, Gian Carlo Cardarilli, Robert Birke, Stefania Perri
2025 C conf
An Anomaly Detection Model for RISC-V in Automotive Applications: A Domain-Specific Accelerator Perspective.
PDP
Elio Vinciguerra, Enrico Russo, Maurizio Palesi, Giuseppe Ascia
2025 J jnl
Assessing the Role of Communication in Modular Multi-Core Quantum Systems.
CoRR
Maurizio Palesi, Enrico Russo, Giuseppe Ascia, Hamaad Rafique, Davide Patti, Vincenzo Catania, Sergi Abadal, Abhijit Das, Pau Escofet, Eduard Alarcón, Carmen G. Almudéver
2025 — conf
Improving Machine Learning Anomaly Detection for Safety-Critical RISC-V Automotive Systems.
CPS Summer School, PhD Workshop
Elio Vinciguerra, Maurizio Palesi, Giuseppe Ascia
2025 — conf
Instruction-Directed MAC for Efficient Classical Communication in Scalable Multi-Chip Quantum Systems.
MCSoC
Maurizio Palesi, Enrico Russo, Hamaad Rafique, Giuseppe Ascia, Davide Patti, Abhijit Das, Sergi Abadal
2025 A conf
Optimizing Qubit Assignment in Modular Quantum Systems via Attention-Based Deep Reinforcement Learning.
DATE
Enrico Russo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania
2024 A* conf
A Deep Reinforcement Learning based Online Scheduling Policy for Deep Neural Network Multi-Tenant Multi-Accelerator Systems.
DAC
Francesco Giulio Blanco, Enrico Russo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania
2024 — conf
Assessing the Role of Communication in Scalable Multi-Core Quantum Architectures.
MCSoC
Maurizio Palesi, Enrico Russo, Davide Patti, Giuseppe Ascia, Vincenzo Catania
2024 J jnl
Attention-Based Deep Reinforcement Learning for Qubit Allocation in Modular Quantum Architectures.
CoRR
Enrico Russo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania
2024 — conf
DNN Hardware Accelerator Selection for Feasible Deployment of MARL-Based MAC Protocols in Industrial IoT Networks.
RTSI
Enrico Russo, Elio Vinciguerra, Giuseppe Ascia, Daniela Panno
2024 — conf
Data-Driven Simulation Based Fault Detection in Automotive RISC-V Applications.
MCSoC
Elio Vinciguerra, Enrico Russo, Maurizio Palesi, Giuseppe Ascia
2024 J jnl
Deep Reinforcement Learning based Online Scheduling Policy for Deep Neural Network Multi-Tenant Multi-Accelerator Systems.
CoRR
Francesco Giulio Blanco, Enrico Russo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania
2024 — conf
Improving LSTM-based Indoor Positioning via Simulation-Augmented Geomagnetic Field Dataset.
MOST
Elio Vinciguerra, Enrico Russo, Maurizio Palesi, Giuseppe Ascia, Hamaad Rafique
2024 C conf
Towards Fair and Firm Real-Time Scheduling in DNN Multi-Tenant Multi-Accelerator Systems via Reinforcement Learning.
ISCAS
Enrico Russo, Francesco Giulio Blanco, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Vincenzo Catania
2024 J jnl
Towards Fair and Firm Real-Time Scheduling in DNN Multi-Tenant Multi-Accelerator Systems via Reinforcement Learning.
CoRR
Enrico Russo, Francesco Giulio Blanco, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Vincenzo Catania
2023 J jnl
A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms.
CoRR
Cristina Silvano, Daniele Ielmini, Fabrizio Ferrandi, Leandro Fiorin, Serena Curzel, Luca Benini, Francesco Conti, Angelo Garofalo, Cristian Zambelli, Enrico Calore, Sebastiano Fabio Schifano, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Stefania Perri, Nicola Petra, Davide De Caro, Luciano Lavagno, Teodoro Urso, Valeria Cardellini, Gian Carlo Cardarilli, Robert Birke
2023 J jnl
A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures.
CoRR
Fabrizio Ferrandi, Serena Curzel, Leandro Fiorin, Daniele Ielmini, Cristina Silvano, Francesco Conti, Alessio Burrello, Francesco Barchi, Luca Benini, Luciano Lavagno, Teodoro Urso, Enrico Calore, Sebastiano Fabio Schifano, Cristian Zambelli, Maurizio Palesi, Giuseppe Ascia, Enrico Russo, Nicola Petra, Davide De Caro, Gennaro Di Meo, Valeria Cardellini, Salvatore Filippone, Francesco Lo Presti, Francesco Silvestri, Paolo Palazzari, Stefania Perri
2023 — conf
Memory-Aware DNN Algorithm-Hardware Mapping via Integer Linear Programming.
CF
Enrico Russo, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Salvatore Monteleone, Vincenzo Catania
2023 J jnl
Multiobjective End-to-End Design Space Exploration of Parameterized DNN Accelerators.
IEEE Internet Things J.
Enrico Russo, Maurizio Palesi, Davide Patti, Salvatore Monteleone, Giuseppe Ascia, Vincenzo Catania
2022 — conf
Combined Application of Approximate Computing Techniques in DNN Hardware Accelerators.
IPDPS Workshops
Enrico Russo, Maurizio Palesi, Davide Patti, Habiba Lahdhiri, Salvatore Monteleone, Giuseppe Ascia, Vincenzo Catania
2022 J jnl
DNN Model Compression for IoT Domain-Specific Hardware Accelerators.
IEEE Internet Things J.
Enrico Russo, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Andrea Mineo, Giuseppe Ascia, Vincenzo Catania
2022 — conf
Exploiting the Approximate Computing Paradigm with DNN Hardware Accelerators.
MECO
Enrico Russo, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Habiba Lahdhiri, Giuseppe Ascia, Vincenzo Catania
2022 A conf
MEDEA: A Multi-objective Evolutionary Approach to DNN Hardware Mapping.
DATE
Enrico Russo, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Giuseppe Ascia, Vincenzo Catania
2021 — conf
LAMBDA: An Open Framework for Deep Neural Network Accelerators Simulation.
PerCom Workshops
Enrico Russo, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Giuseppe Ascia, Vincenzo Catania
2020 C conf
DNNZip: Selective Layers Compression Technique in Deep Neural Network Accelerators.
DSD
Habiba Lahdhiri, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Giuseppe Ascia, Jordane Lorandel, Emmanuelle Bourdel, Vincenzo Catania
2020 J jnl
Exploiting Data Resilience in Wireless Network-on-chip Architectures.
ACM J. Emerg. Technol. Comput. Syst.
Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti, John Jose, Valerio Mario Salerno
2020 — conf
Improving Inference Latency and Energy of DNNs through Wireless Enabled Multi-Chip-Module-based Architectures and Model Parameters Compression.
NOCS
Giuseppe Ascia, Vincenzo Catania, Andrea Mineo, Salvatore Monteleone, Maurizio Palesi, Davide Patti
2020 — conf
Improving Inference Latency and Energy of Network-on-Chip based Convolutional Neural Networks through Weights Compression.
IPDPS Workshops
Giuseppe Ascia, Vincenzo Catania, John Jose, Salvatore Monteleone, Maurizio Palesi, Davide Patti
2019 — conf
Analyzing networks-on-chip based deep neural networks.
NOCS
Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti, John Jose
2019 — conf
Networks-on-Chip based Deep Neural Networks Accelerators for IoT Edge Devices.
IoTSMS
Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti, John Jose
2018 — conf
Approximate Wireless Networks-on-Chip.
DCIS
Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti, John Jose
2018 — conf
Improving energy consumption of NoC based architectures through approximate communication.
MECO
Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti, John Jose
2016 J jnl
Exploiting antenna directivity in wireless NoC architectures.
Microprocess. Microsystems
Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania
2016 C conf
Making Android Apps Data-Leak-Safe by Data Flow Analysis and Code Injection.
WETICE
Giuseppe Ascia, Vincenzo Catania, Raffaele Di Natale, Andrea Fornaia, Misael Mongiovì, Salvatore Monteleone, Giuseppe Pappalardo, Emiliano Tramontana
2016 J jnl
On-Chip Communication Energy Reduction Through Reliability Aware Adaptive Voltage Swing Scaling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Partha Pratim Pande, Vincenzo Catania
2016 J jnl
Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures.
IEEE Trans. Very Large Scale Integr. Syst.
Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania
2015 A conf
A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures.
DATE
Andrea Mineo, Mohd Shahrizal Rusli, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania, Muhammad N. Marsono
2015 J jnl
Coupling Routing Algorithm and Data Encoding for Low Power Networks on Chip.
J. Comput. Sci.
Maurizio Palesi, Davide Patti, Giuseppe Ascia, Daniela Panno, Vincenzo Catania
2014 — conf
A Closed Loop Control based Power Manager for WiNoC Architectures.
MES
Mohd Shahrizal Rusli, Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania, Muhammad N. Marsono
2014 A conf
An adaptive transmitting power technique for energy efficient mm-wave wireless NoCs.
DATE
Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania
2013 J jnl
A fuzzy system index to preserve interpretability in deep tuning of fuzzy rule based classifiers.
J. Intell. Fuzzy Syst.
Alessandro G. Di Nuovo, Giuseppe Ascia
2013 C conf
An Adaptive Output Selection Function Based on a Fuzzy Rule Base System for Network on Chip.
DSD
Giuseppe Ascia, Maurizio Palesi, Vincenzo Catania
2013 — conf
Low Energy Mapping Techniques under Reliability and Bandwidth Constraints.
HPCC/EUC
Andrea Mineo, Marina Masi, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania
2013 — conf
NoC links energy reduction through link voltage scaling.
ICSAMOS
Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania
2013 C conf
Runtime Online Links Voltage Scaling for Low Energy Networks on Chip.
DSD
Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania
2012 — conf
A Study on Evolutionary Multi-Objective Optimization with Fuzzy Approximation for Computational Expensive Problems.
PPSN (2)
Alessandro G. Di Nuovo, Giuseppe Ascia, Vincenzo Catania
2011 J jnl
Data Encoding Schemes in Networks on Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Maurizio Palesi, Giuseppe Ascia, Fabrizio Fazzino, Vincenzo Catania
2011 J jnl
Performance evaluation of efficient multi-objective evolutionary algorithms for design space exploration of embedded computer systems.
Appl. Soft Comput.
Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti
2009 C conf
Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip.
DSD
Maurizio Palesi, Fabrizio Fazzino, Giuseppe Ascia, Vincenzo Catania
2008 J jnl
Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip.
IEEE Trans. Computers
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
2007 J jnl
Efficient design space exploration for application specific systems-on-a-chip.
J. Syst. Archit.
Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti
2006 J jnl
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip.
J. Univers. Comput. Sci.
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
2006 B conf
A Multiobjective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design.
IEEE Congress on Evolutionary Computation
Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti
2006 — conf
An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design.
ICSAMOS
Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti
2006 J jnl
An integrated fuzzy-GA approach for buffer management.
IEEE Trans. Fuzzy Syst.
Giuseppe Ascia, Vincenzo Catania, Daniela Panno
2006 Misc conf
Fuzzy decision making in embedded system design.
CODES+ISSS
Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania
2006 — conf
Neighbors-on-Path: A New Selection Strategy for On-Chip Networks.
ESTIMedia
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
2005 J jnl
A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
2005 — conf
A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems.
ASP-DAC
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
2005 B conf
An evolutionary approach to network-on-chip mapping problem.
Congress on Evolutionary Computation
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
2005 J jnl
An evolutionary management scheme in high-performance packet switches.
IEEE/ACM Trans. Netw.
Giuseppe Ascia, Vincenzo Catania, Daniela Panno
2005 — conf
Exploring Design Space of VLIW Architectures.
ASAP
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
2005 — conf
Hyperblock formation: a power/energy perspective for high performance VLIW architectures.
ISCAS (4)
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
2004 J jnl
A GA-based design space exploration framework for parameterized system-on-a-chip platforms.
IEEE Trans. Evol. Comput.
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
2004 — conf
Multi-objective Optimization of a Parameterized VLIW Architecture.
Evolvable Hardware
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
2004 Misc conf
Multi-objective mapping for mesh-based NoC architectures.
CODES+ISSS
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
2003 C conf
A Genetic Approach To Bus Encoding.
VLSI-SOC
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
2003 — conf
A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems.
PATMOS
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
2003 — conf
An evolutionary approach for reducing the energy in address buses.
ISICT
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Antonio Parlato
2003 B conf
An evolutionary approach for reducing the switching activity in address buses.
IEEE Congress on Evolutionary Computation
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Antonio Parlato
2003 — conf
EPIC-Explorer: A Parameterized VLIW-based Platform Framework for Design Space Exploration.
ESTIMedia
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
2002 — conf
A Framework for Design Space Exploration of Parameterized VLSI Systems.
ASP-DAC/VLSI Design
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
2002 A* conf
An efficient buffer management policy based on an integrated Fuzzy-GA approach.
INFOCOM
Giuseppe Ascia, Vincenzo Catania, Daniela Panno
2001 A* conf
A Fuzzy Buffer Management Scheme For ATM and IP Networks.
INFOCOM
Giuseppe Ascia, Vincenzo Catania, Giuseppe Ficili, Daniela Panno
2001 B conf
A General Purpose Processor Oriented Fuzzy Reasoning.
FUZZ-IEEE
Giuseppe Ascia, Vincenzo Catania
2001 C conf
An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms.
VLSI-SOC
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
2001 J jnl
An Instruction-Level Power Analysis Model with Data Dependency.
VLSI Design
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Sarta
2001 Misc conf
An adaptive fuzzy threshold scheme for high performance shared-memory switches.
SAC
Giuseppe Ascia, Vincenzo Catania, Daniela Panno
2001 J jnl
An efficient fuzzy system for traffic management in high-speed packet-switched networks.
Soft Comput.
Giuseppe Ascia, Vincenzo Catania, Daniela Panno
2001 — conf
Parameterised system design based on genetic algorithms.
CODES
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
2000 B conf
A pipeline parallel architecture for a fuzzy inference processor.
FUZZ-IEEE
Giuseppe Ascia, Vincenzo Catania
1999 — conf
An Optimized Parallel RISC Processor for Fuzzy Computing.
Applied Informatics
Giuseppe Ascia, Vincenzo Catania
1999 J jnl
VLSI hardware architecture for complex fuzzy systems.
IEEE Trans. Fuzzy Syst.
Giuseppe Ascia, Vincenzo Catania, Marco Russo
1998 Misc conf
A Framework for a Parallel Architecture Dedicated to Soft Computing.
VLSI Design
Giuseppe Ascia, Vincenzo Catania
1997 J jnl
A VLSI fuzzy expert system for real-time traffic control in ATM networks.
IEEE Trans. Fuzzy Syst.
Giuseppe Ascia, Vincenzo Catania, Giuseppe Ficili, Sergio Palazzo, Daniela Panno
1997 Misc conf
Design of a VLSI Hardware PET Decoder.
VLSI Design
Giuseppe Ascia, Vincenzo Catania, Giuseppe Ficili
1996 J jnl
A Reconfigurable Parallel Architecture for a Fuzzy Processor.
Inf. Sci.
Giuseppe Ascia, Vincenzo Catania, Antonio Puliafito, Lorenzo Vita
1996 J jnl
An Efficient Hardware Architecture to Support Complex Fuzzy Reasoning.
Int. J. Artif. Intell. Tools
Giuseppe Ascia, Vincenzo Catania
1995 J jnl
A VLSI Parallel Architecture for Fuzzy Expert Systems.
Int. J. Pattern Recognit. Artif. Intell.
Vincenzo Catania, Giuseppe Ascia
1995 B conf
An efficient hardware architecture to support complex fuzzy reasoning.
ICTAI
Giuseppe Ascia, Vincenzo Catania
1995 B conf
Design of a VLSI fuzzy processor for ATM traffic sources management.
LCN
Giuseppe Ascia, Giuseppe Ficili, Daniela Panno
1995 Misc conf
Design of a VLSI parallel processor for fuzzy computing.
VLSI Design
Giuseppe Ascia, Vincenzo Catania
1995 J jnl
Designing for parallel fuzzy computing.
IEEE Micro
Giuseppe Ascia, Vincenzo Catania, Biagio Giacalone, Marco Russo, Lorenzo Vita
1995 J jnl
Fuzzy Hardware Challenges.
IEEE Micro
Abraham Kandel, Giuseppe Ascia, Vincenzo Catania, Biagio Giacalone, Marco Russo, Lorenzo Vita, Andrés Jaramillo-Botero, Yoichi Miyake, Hua Harry Li, Nowell Godfrey, Yuandong Ji, Shuwei Guo, Liliane Peters, Krishna Rao Valavala, Mahmoud A. Manzoul, Antonio Ruiz, Julio Gutiérrez, Felipe Fernández