Girish Pahwa

19 papers A* 2A 2Journal 8Unranked 7
YearRankTypeTitle / Venue / Authors
2025 A conf
Pushing the Boundaries of AI Chips: From Monolithic 3D CMOS to Cryogenic Computing.
DATE
Mahdi Benkhelifa, Shivendra Singh Parihar, Anirban Kar, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch
2024 — conf
Impact of Self-Heating in 5nm FinFETs at Cryogenic Temperatures for Reliable Quantum Computing: Device-Circuit Interaction.
IRPS
Shivendra Singh Parihar, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch
2024 — conf
Technology Mapping for Cryogenic CMOS Circuits.
ISVLSI
Benjamin Hien, Marcel Walter, Victor M. van Santen, Florian Klemme, Shivendra Singh Parihar, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch, Robert Wille
2023 — conf
5nm FinFET Cryogenic SRAM Evaluation for Quantum Computing.
DRC
Shivendra Singh Parihar, Simon Thomann, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch
2023 J jnl
Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shivendra Singh Parihar, Victor M. van Santen, Simon Thomann, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch
2023 J jnl
Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs.
IEEE Open J. Circuits Syst.
Shivendra Singh Parihar, Simon Thomann, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch
2023 A* conf
Design Automation for Cryogenic CMOS Circuits.
DAC
Victor M. van Santen, Marcel Walter, Florian Klemme, Shivendra Singh Parihar, Girish Pahwa, Yogesh Singh Chauhan, Robert Wille, Hussam Amrouch
2023 J jnl
FerroX: A GPU-accelerated, 3D phase-field simulation framework for modeling ferroelectric devices.
Comput. Phys. Commun.
Prabhat Kumar, Andrew Nonaka, Revathi Jambunathan, Girish Pahwa, Sayeef S. Salahuddin, Zhi Yao
2023 J jnl
Robust Compact Model of High-Voltage MOSFET's Drift Region.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Girish Pahwa, Ayushi Sharma, Ravi Goel, Garima Gill, Harshit Agarwal, Yogesh Singh Chauhan, Chenming Hu
2022 — conf
Compact Model for Trap Assisted Tunneling based GIDL.
DRC
Chetan K. Dabhi, Girish Pahwa, Sayeef S. Salahuddin, Chenming Hu
2022 J jnl
FerroX : A GPU-accelerated, 3D Phase-Field Simulation Framework for Modeling Ferroelectric Devices.
CoRR
Prabhat Kumar, Andrew Nonaka, Revathi Jambunathan, Girish Pahwa, Sayeef S. Salahuddin, Zhi Yao
2021 J jnl
On the Resiliency of NCFET Circuits Against Voltage Over-Scaling.
IEEE Trans. Circuits Syst. I Regul. Pap.
Guilherme Paim, Georgios Zervakis, Girish Pahwa, Yogesh Singh Chauhan, Eduardo Antonio Cesar da Costa, Sergio Bampi, Jörg Henkel, Hussam Amrouch
2020 — conf
Impact of Radiation on Negative Capacitance FinFET.
IRPS
Govind Bajpai, Aniket Gupta, Om Prakash, Girish Pahwa, Jörg Henkel, Yogesh Singh Chauhan, Hussam Amrouch
2020 J jnl
Impact of Variability on Processor Performance in Negative Capacitance FinFET Technology.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hussam Amrouch, Girish Pahwa, Amol D. Gaidhane, Chetan K. Dabhi, Florian Klemme, Om Prakash, Yogesh Singh Chauhan
2020 — conf
NCFET to Rescue Technology Scaling: Opportunities and Challenges.
ASP-DAC
Hussam Amrouch, Victor M. van Santen, Girish Pahwa, Yogesh Singh Chauhan, Jörg Henkel
2019 A conf
NCFET-Aware Voltage Scaling.
ISLPED
Sami Salamin, Martin Rapp, Hussam Amrouch, Girish Pahwa, Yogesh Singh Chauhan, Jörg Henkel
2019 A* conf
Performance, Power and Cooling Trade-Offs with NCFET-based Many-Cores.
DAC
Martin Rapp, Sami Salamin, Hussam Amrouch, Girish Pahwa, Yogesh Singh Chauhan, Jörg Henkel
2018 J jnl
Negative Capacitance Transistor to Address the Fundamental Limitations in Technology Scaling: Processor Performance.
IEEE Access
Hussam Amrouch, Girish Pahwa, Amol D. Gaidhane, Jörg Henkel, Yogesh Singh Chauhan
2016 — conf
Designing energy efficient and hysteresis free negative capacitance FinFET with negative DIBL and 3.5X ION using compact modeling approach.
ESSCIRC
Girish Pahwa, Tapas Dutta, Amit Agarwal, Yogesh Singh Chauhan