Giovanni Ansaloni

97 papers A* 3A 13C 8Misc 4Journal 43Unranked 26

Year	Rank	Type	Title / Venue / Authors
2025	C	`conf`	A Reconfigurable High-Dynamic Range ∆Σ Front-End with Event-Based Decimation for Bandwidth-Efficient Implantable Neural Interfaces. ISCAS Natalia Martínez, Juan Sapriza, Pasquale Davide Schiavone, Giovanni Ansaloni, Luke Bashford, Andrew Jackson, David Atienza, Timothy G. Constandinou
2025	—	`conf`	A flexible framework for early power and timing comparison of time-multiplexed CGRA kernel executions. CF (Companion) Maxime Henri Aspros, Juan Sapriza, Giovanni Ansaloni, David Atienza
2025	J	`jnl`	A flexible framework for early power and timing comparison of time-multiplexed CGRA kernel executions. CoRR Maxime Henri Aspros, Juan Sapriza, Giovanni Ansaloni, David Atienza
2025	J	`jnl`	ACE: Automated Optimization Towards Iterative Classification in Edge Health Monitors. IEEE Trans. Biomed. Circuits Syst. Yuxuan Wang, Lara Orlandic, Simone Machetti, Giovanni Ansaloni, David Atienza
2025	—	`conf`	An MLIR-Based Compilation Framework for CGRA Application Deployment. ARC Yuxuan Wang, Cristian Tirelli, Lara Orlandic, Juan Sapriza, Rubén Rodríguez Álvarez, Giovanni Ansaloni, Laura Pozzi, David Atienza
2025	J	`jnl`	An MLIR-based Compilation Framework for Control Flow Management on CGRAs. CoRR Yuxuan Wang, Cristian Tirelli, Giovanni Ansaloni, Laura Pozzi, David Atienza
2025	—	`conf`	HEEPstor: an Open-Hardware Co-design Framework for Quantized Machine Learning at the Edge. CF (Companion) Pedro Palacios, Rafael Medina, Giovanni Ansaloni, David Atienza
2025	—	`conf`	Keep All in Memory with Maxwell: A Near-SRAM Computing Architecture for Edge AI Applications. ISQED Grégoire Eggermann, Giovanni Ansaloni, David Atienza
2025	J	`jnl`	LionHeart: A Layer-Based Mapping Framework for Heterogeneous Systems With Analog In-Memory Computing Tiles. IEEE Trans. Emerg. Top. Comput. Corey Lammie, Yuxuan Wang, Flavio Ponzina, Joshua Alexander Harrison Klein, Hadjer Benmeziane, Marina Zapater, Irem Boybat, Abu Sebastian, Giovanni Ansaloni, David Atienza
2025	J	`jnl`	Personalization on a Budget: Minimally-Labeled Continual Learning for Resource-Efficient Seizure Detection. CoRR Amirhossein Shahbazinia, Jonathan Dan, José Angel Miranda, Giovanni Ansaloni, David Atienza
2025	J	`jnl`	Physical Design Exploration of a Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes. CoRR Lorenzo Ruotolo, Lara Orlandic, Pengbo Yu, Moritz Brunion, Daniele Jahier Pagliari, Dwaipayan Biswas, Giovanni Ansaloni, David Atienza, Julien Ryckaert, Francky Catthoor, Yukai Chen
2025	J	`jnl`	SideDRAM: Integrating SoftSIMD Datapaths near DRAM Banks for Energy-Efficient Variable Precision Computation. ACM Trans. Embed. Comput. Syst. Rafael Medina Morillas, Pengbo Yu, Alexandre Levisse, Dwaipayan Biswas, Marina Zapater, Giovanni Ansaloni, Francky Catthoor, David Atienza
2025	A	`conf`	Structured pruning for efficient systolic array accelerated cascade Speech-to-Text Translation. INTERSPEECH Jean-Luc Rouas, Charles Brazier, Leila Ben Letaifa, Rafael Medina, Pedro Palacios, David Atienza, Giovanni Ansaloni
2025	—	`conf`	Systolic Arrays and Structured Pruning Co-design for Efficient Transformers in Edge Systems. ACM Great Lakes Symposium on VLSI Pedro Palacios, Rafael Medina, Jean-Luc Rouas, Giovanni Ansaloni, David Atienza
2025	J	`jnl`	Towards Accurate RISC-V Full System Simulation via Component-Level Calibration. ACM Trans. Embed. Comput. Syst. Karan Pathak, Joshua Alexander Harrison Klein, Giovanni Ansaloni, Said Hamdioui, Georgi Gaydadjiev, Marina Zapater, David Atienza
2025	—	`conf`	X-HEEP: An Open-Source, Configurable and Extendible RISC-V Platform for TinyAI Applications. ISVLSI Simone Machetti, Pasquale Davide Schiavone, Giovanni Ansaloni, Miguel Peón-Quirós, David Atienza
2025	J	`jnl`	X-HEEP: An Open-Source, Configurable and Extendible RISC-V Platform for TinyAI Applications. CoRR Simone Machetti, Pasquale Davide Schiavone, Giovanni Ansaloni, Miguel Peón-Quirós, David Atienza
2025	J	`jnl`	e-GPU: An Open-Source and Configurable RISC-V Graphic Processing Unit for TinyAI Applications. CoRR Simone Machetti, Pasquale Davide Schiavone, Lara Orlandic, Darong Huang, Deniz Kasap, Giovanni Ansaloni, David Atienza
2024	—	`conf`	Accelerator-Driven Data Arrangement to Minimize Transformers Run-Time on Multi-Core Architectures. PARMA-DITAM Alireza Amirshahi, Giovanni Ansaloni, David Atienza
2024	J	`jnl`	An Energy Efficient Soft SIMD Microarchitecture and Its Application on Quantized CNNs. IEEE Trans. Very Large Scale Integr. Syst. Pengbo Yu, Flavio Ponzina, Alexandre Levisse, Mohit Gupta, Dwaipayan Biswas, Giovanni Ansaloni, David Atienza, Francky Catthoor
2024	J	`jnl`	Bank on Compute-Near-Memory: Design Space Exploration of Processing-Near-Bank Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rafael Medina, Giovanni Ansaloni, Marina Zapater, Alexandre Levisse, Saeideh Alinezhad Chamazcoti, Timon Evenblij, Dwaipayan Biswas, Francky Catthoor, David Atienza
2024	A	`conf`	Cross-layer Exploration of 2.5D Energy-Efficient Heterogeneous Chiplets Integration: From System Simulation to Open Hardware. ISLPED Anna Burdina, Gabriel Catel Torres, Pasquale Davide Schiavone, Miguel Peón-Quirós, Giovanni Ansaloni, David Atienza, Marina Zapater
2024	—	`conf`	DBFS: Dynamic Bitwidth-Frequency Scaling for Efficient Software-defined SIMD. ISVLSI Pengbo Yu, Flavio Ponzina, Alexandre Levisse, Dwaipayan Biswas, Giovanni Ansaloni, David Atienza, Francky Catthoor
2024	A	`conf`	FVLLMONTI: The 3D Neural Network Compute Cube $(N^{2}C^{2})$ Concept for Efficient Transformer Architectures Towards Speech-to-Speech Translation. DATE Ian O'Connor, Sara Mannaa, Alberto Bosio, Bastien Deveautour, Damien Deleruyelle, Tetiana Obukhova, Cédric Marchand, Jens Trommer, Çigdem Çakirlar, Bruno Neckel Wesling, Thomas Mikolajick, Oskar Baumgartner, Mischa Thesberg, David Pirker, Christoph Lenz, Zlatan Stanojevic, Markus Karner, Guilhem Larrieu, Sylvain Pelloquin, Konstantinous Moustakas, Jonas Müller, Giovanni Ansaloni, Alireza Amirshahi, David Atienza, Jean-Luc Rouas, Leila Ben Letaifa, Georgeta Bordeall, Charles Brazier, Chhandak Mukherjee, Marina Deng, Yifan Wang, Marc François, Houssem Rezgui, Reveil Lucas, Cristell Maneux
2024	J	`jnl`	LionHeart: A Layer-based Mapping Framework for Heterogeneous Systems with Analog In-Memory Computing Tiles. CoRR Corey Lammie, Flavio Ponzina, Yuxuan Wang, Joshua Alexander Harrison Klein, Marina Zapater, Irem Boybat, Abu Sebastian, Giovanni Ansaloni, David Atienza
2024	J	`jnl`	MetaWearS: A Shortcut in Wearable Systems Lifecycle with Only a Few Shots. CoRR Alireza Amirshahi, Maedeh H. Toosi, Siamak Mohammadi, Stefano Albini, Pasquale Davide Schiavone, Giovanni Ansaloni, Amir Aminifar, David Atienza
2024	—	`conf`	Resource-Efficient Continual Learning for Personalized Online Seizure Detection. EMBC Amirhossein Shahbazinia, Flavio Ponzina, José Angel Miranda, Jonathan Dan, Giovanni Ansaloni, David Atienza
2024	J	`jnl`	SAT-Based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs. ACM J. Emerg. Technol. Comput. Syst. Cristian Tirelli, Juan Sapriza, Rubén Rodríguez Álvarez, Lorenzo Ferretti, Benoît W. Denkinger, Giovanni Ansaloni, José Angel Miranda, David Atienza, Laura Pozzi
2024	J	`jnl`	SAT-based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs. CoRR Cristian Tirelli, Juan Sapriza, Rubén Rodríguez Álvarez, Lorenzo Ferretti, Benoît W. Denkinger, Giovanni Ansaloni, José Angel Miranda Calero, David Atienza, Laura Pozzi
2024	J	`jnl`	Systolic Arrays and Structured Pruning Co-design for Efficient Transformers in Edge Systems. CoRR Pedro Palacios, Rafael Medina, Jean-Luc Rouas, Giovanni Ansaloni, David Atienza
2024	J	`jnl`	Which Coupled is Best Coupled? An Exploration of AIMC Tile Interfaces and Load Balancing for CNNs. IEEE Trans. Parallel Distributed Syst. Joshua Alexander Harrison Klein, Irem Boybat, Giovanni Ansaloni, Marina Zapater, David Atienza
2023	C	`conf`	A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication. VLSI-SoC Grégoire Eggermann, Marco Rios, Giovanni Ansaloni, Sani R. Nassif, David Atienza
2023	J	`jnl`	ALPINE: Analog In-Memory Acceleration With Tight Processor Integration for Deep Learning. IEEE Trans. Computers Joshua Alexander Harrison Klein, Irem Boybat, Yasir Mahmood Qureshi, Martino Dazzi, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, Abu Sebastian, David Atienza
2023	J	`jnl`	Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures. CoRR Alireza Amirshahi, Giovanni Ansaloni, David Atienza
2023	—	`conf`	An Open-Hardware Coarse-Grained Reconfigurable Array for Edge Computing. CF Rubén Rodríguez Álvarez, Benoît W. Denkinger, Juan Sapriza, José Angel Miranda Calero, Giovanni Ansaloni, David Atienza Alonso
2023	J	`jnl`	Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference. IEEE Trans. Emerg. Top. Comput. Marco Rios, Flavio Ponzina, Alexandre Levisse, Giovanni Ansaloni, David Atienza
2023	A	`conf`	Cross Layer Design for the Predictive Assessment of Technology-Enabled Architectures. DATE Michael T. Niemier, Xiaobo Sharon Hu, Liu Liu, Mohammad Mehdi Sharifi, Ian O'Connor, David Atienza, Giovanni Ansaloni, Can Li, Asif Khan, Daniel C. Ralph
2023	J	`jnl`	Event-based sampled ECG morphology reconstruction through self-similarity. Comput. Methods Programs Biomed. Silvio Zanoli, Giovanni Ansaloni, Tomás Teijeiro, David Atienza
2023	J	`jnl`	Overflow-free Compute Memories for Edge AI Acceleration. ACM Trans. Embed. Comput. Syst. Flavio Ponzina, Marco Rios, Alexandre Levisse, Giovanni Ansaloni, David Atienza
2023	C	`conf`	REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal. VLSI-SoC Rafael Medina, Darong Huang, Giovanni Ansaloni, Marina Zapater, David Atienza
2023	—	`conf`	System-Level Exploration of In-Package Wireless Communication for Multi-Chiplet Platforms. ASP-DAC Rafael Medina, Joshua Kein, Giovanni Ansaloni, Marina Zapater, Sergi Abadal, Eduard Alarcón, David Atienza
2023	J	`jnl`	Thermal and Voltage-Aware Performance Management of 3-D MPSoCs With Flow Cell Arrays and Integrated SC Converters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Halima Najibi, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, Miroslav Vasic, David Atienza
2023	—	`conf`	TiC-SAT: Tightly-Coupled Systolic Accelerator for Transformers. ASP-DAC Alireza Amirshahi, Joshua Alexander Harrison Klein, Giovanni Ansaloni, David Atienza
2022	J	`jnl`	A Formal Framework for Maximum Error Estimation in Approximate Logic Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi
2022	J	`jnl`	A Hardware/Software Co-Design Vision for Deep Learning at the Edge. IEEE Micro Flavio Ponzina, Simone Machetti, Marco Rios, Benoît Walter Denkinger, Alexandre Levisse, Giovanni Ansaloni, Miguel Peón-Quirós, David Atienza
2022	J	`jnl`	A Soft SIMD Based Energy Efficient Computing Microarchitecture. CoRR Pengbo Yu, Alexandre Levisse, Mohit Gupta, Timon Evenblij, Giovanni Ansaloni, Francky Catthoor, David Atienza
2022	J	`jnl`	ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning. CoRR Joshua Alexander Harrison Klein, Irem Boybat, Yasir Mahmood Qureshi, Martino Dazzi, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, Abu Sebastian, David Atienza
2022	—	`conf`	An Accuracy-Driven Compression Methodology to Derive Efficient Codebook-Based CNNs. COINS Flavio Ponzina, Miguel Peón-Quirós, Giovanni Ansaloni, David Atienza
2022	J	`jnl`	Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference. CoRR Marco Rios, Flavio Ponzina, Alexandre Levisse, Giovanni Ansaloni, David Atienza
2022	—	`conf`	Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge. ACM Great Lakes Symposium on VLSI Marco Rios, Flavio Ponzina, Giovanni Ansaloni, Alexandre Levisse, David Atienza
2022	—	`conf`	Full System Exploration of On-Chip Wireless Communication on Many-Core Architectures. LASCAS Rafael Medina, Joshua Kein, Yasir Mahmood Qureshi, Marina Zapater, Giovanni Ansaloni, David Atienza
2022	A	`conf`	INCLASS: Incremental Classification Strategy for Self-Aware Epileptic Seizure Detection. DATE Lorenzo Ferretti, Giovanni Ansaloni, Renaud Marquis, Tomás Teijeiro, Philippe Ryvlin, David Atienza, Laura Pozzi
2022	—	`conf`	Thermal and Power-Aware Run-time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays. ACM Great Lakes Symposium on VLSI Halima Najibi, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, David Atienza
2021	—	`conf`	A Flexible In-Memory Computing Architecture for Heterogeneously Quantized CNNs. ISVLSI Flavio Ponzina, Marco Rios, Giovanni Ansaloni, Alexandre Levisse, David Atienza
2021	—	`conf`	Architecting more than Moore: wireless plasticity for massive heterogeneous computer architectures (WiPLASH). CF Joshua Alexander Harrison Klein, Alexandre Levisse, Giovanni Ansaloni, David Atienza, Marina Zapater, Martino Dazzi, Geethan Karunaratne, Irem Boybat, Abu Sebastian, Davide Rossi, Francesco Conti, Elana Pereira de Santana, Peter Haring Bolívar, Mohamed Saeed, Renato Negra, Zhenxing Wang, Kun-Ta Wang, Max Christian Lemme, Akshay Jain, Robert Guirado, Hamidreza Taghvaee, Sergi Abadal
2021	J	`jnl`	Cluster-Based Heuristic for High Level Synthesis Design Space Exploration. IEEE Trans. Emerg. Top. Comput. Lorenzo Ferretti, Giovanni Ansaloni, Laura Pozzi
2021	J	`jnl`	DB4HLS: A Database of High-Level Synthesis Design Space Explorations. CoRR Lorenzo Ferretti, Jihye Kwon, Giovanni Ansaloni, Giuseppe Di Guglielmo, Luca P. Carloni, Laura Pozzi
2021	J	`jnl`	DB4HLS: A Database of High-Level Synthesis Design Space Explorations. IEEE Embed. Syst. Lett. Lorenzo Ferretti, Jihye Kwon, Giovanni Ansaloni, Giuseppe Di Guglielmo, Luca P. Carloni, Laura Pozzi
2021	A*	`conf`	Exact Neural Networks from Inexact Multipliers via Fibonacci Weight Encoding. DAC William Andrew Simon, Valérian Ray, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, David Atienza
2021	A	`conf`	Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing. DATE Marco Rios, Flavio Ponzina, Giovanni Ansaloni, Alexandre Levisse, David Atienza
2020	J	`jnl`	Approximate Logic Synthesis: A Survey. Proc. IEEE Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi, Sherief Reda
2020	—	`conf`	Judiciously Spreading Approximation Among Arithmetic Components with Top-Down Inexact Hardware Design. ARC Giovanni Ansaloni, Ilaria Scarabottolo, Laura Pozzi
2020	J	`jnl`	Leveraging Prior Knowledge for Effective Design-Space Exploration in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lorenzo Ferretti, Jihye Kwon, Giovanni Ansaloni, Giuseppe Di Guglielmo, Luca P. Carloni, Laura Pozzi
2019	C	`conf`	Compiler-Assisted Selection of Hardware Acceleration Candidates from Application Source Code. ICCD Georgios Zacharopoulos, Lorenzo Ferretti, Giovanni Ansaloni, Giuseppe Di Guglielmo, Luca P. Carloni, Laura Pozzi
2019	A*	`conf`	Partition and Propagate: an Error Derivation Algorithm for the Design of Approximate Circuits. DAC Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi
2019	J	`jnl`	RegionSeeker: Automatically Identifying and Selecting Accelerators From Application Source Code. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Georgios Zacharopoulos, Lorenzo Ferretti, Emanuele Giaquinta, Giovanni Ansaloni, Laura Pozzi
2019	A	`conf`	Tailoring SVM Inference for Resource-Efficient ECG-Based Epilepsy Monitors. DATE Lorenzo Ferretti, Giovanni Ansaloni, Laura Pozzi, Amir Aminifar, David Atienza, Leila Cammoun, Philippe Ryvlin
2019	J	`jnl`	i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-Signal Processing. IEEE Embed. Syst. Lett. Loris Duch, Soumya Basu, Miguel Peón-Quirós, Giovanni Ansaloni, Laura Pozzi, David Atienza
2018	Misc	`conf`	A partitioning strategy for exploring error-resilience in circuits: work-in-progress. CASES Ilaria Scarabottolo, Giovanni Ansaloni, Laura Pozzi
2018	A	`conf`	Circuit carving: A methodology for the design of approximate hardware. DATE Ilaria Scarabottolo, Giovanni Ansaloni, Laura Pozzi
2018	C	`conf`	Heterogeneous and Inexact: Maximizing Power Efficiency of Edge Computing Sensors for Health Monitoring Applications. ISCAS Soumya Basu, Loris Duch, Miguel Peón-Quirós, David Atienza, Giovanni Ansaloni, Laura Pozzi
2018	C	`conf`	Lattice-Traversing Design Space Exploration for High Level Synthesis. ICCD Lorenzo Ferretti, Giovanni Ansaloni, Laura Pozzi
2018	—	`conf`	Machine Learning Approach for Loop Unrolling Factor Prediction in High Level Synthesis. HPCS Georgios Zacharopoulos, Andrea Barbon, Giovanni Ansaloni, Laura Pozzi
2017	J	`jnl`	A Synchronization-Based Hybrid-Memory Multi-Core Architecture for Energy-Efficient Biomedical Signal Processing. IEEE Trans. Computers Rubén Braojos, Daniele Bortolotti, Andrea Bartolini, Giovanni Ansaloni, Luca Benini, David Atienza
2017	J	`jnl`	An Inexact Ultra-low Power Bio-signal Processing Architecture With Lightweight Error Recovery. ACM Trans. Embed. Comput. Syst. Soumya Basu, Loris Duch, Rubén Braojos, Giovanni Ansaloni, Laura Pozzi, David Atienza
2017	J	`jnl`	HEAL-WEAR: An Ultra-Low Power Heterogeneous System for Bio-Signal Analysis. IEEE Trans. Circuits Syst. I Regul. Pap. Loris Duch, Soumya Basu, Rubén Braojos, Giovanni Ansaloni, Laura Pozzi, David Atienza
2016	—	`conf`	A multi-core reconfigurable architecture for ultra-low power bio-signal analysis. BioCAS Loris Duch, Soumya Basu, Rubén Braojos, David Atienza, Giovanni Ansaloni, Laura Pozzi
2016	J	`jnl`	Inexact-aware architecture design for ultra-low power bio-signal analysis. IET Comput. Digit. Tech. Soumya Basu, Pablo García Del Valle, Georgios Karakonstantis, Giovanni Ansaloni, Laura Pozzi, David Atienza
2016	Misc	`conf`	Nano-engineered architectures for ultra-low power wireless body sensor nodes. CODES+ISSS Rubén Braojos, David Atienza, Mohamed M. Sabry Aly, Tony F. Wu, H.-S. Philip Wong, Subhasish Mitra, Giovanni Ansaloni
2016	—	`conf`	PHIDIAS: ultra-low-power holistic design for smart bio-signals computing platforms. Conf. Computing Frontiers Daniele Bortolotti, Andrea Bartolini, Luca Benini, V. Rajesh Pamula, Nick Van Helleputte, Chris Van Hoof, Marian Verhelst, Tobias Gemmeke, Rubén Braojos Lopez, Giovanni Ansaloni, David Atienza, Pierre Vandergheynst
2015	—	`conf`	Heterogeneous Error-Resilient Scheme for Spectral Analysis in Ultra-Low Power Wearable Electrocardiogram Devices. ISVLSI Soumya Basu, Pablo García Del Valle, Georgios Karakonstantis, Giovanni Ansaloni, David Atienza
2014	J	`jnl`	Early Classification of Pathological Heartbeats on Wireless Body Sensor Nodes. Sensors Rubén Braojos, Ivan Beretta, Giovanni Ansaloni, David Atienza
2014	A	`conf`	Hardware/software approach for code synchronization in low-power multi-core sensor nodes. DATE Rubén Braojos, Ahmed Yasir Dogan, Ivan Beretta, Giovanni Ansaloni, David Atienza
2014	—	`conf`	Live demonstration: ECG sensor interface in a low power SoC for wireless portable ECG monitoring. BioCAS Frédéric Giroud, Pascal Persechini, Pierre-François Ruedi, Giovanni Ansaloni, Rubén Braojos, F. Viemon, Frederic Masson
2014	Misc	`conf`	Power-efficient joint compressed sensing of multi-lead ECG signals. ICASSP Hossein Mamaghanian, Giovanni Ansaloni, David Atienza, Pierre Vandergheynst
2014	—	`conf`	Risk Assessment of Atrial Fibrillation: a Failure Prediction Approach. CinC Jelena Milosevic, Andreas Dittrich, Alberto Ferrante, Miroslaw Malek, Camilo Rojas Quiros, Rubén Braojos, Giovanni Ansaloni, David Atienza
2014	A*	`conf`	Ultra-Low Power Design of Wearable Cardiac Monitoring Systems. DAC Rubén Braojos, Hossein Mamaghanian, Alair Dias Junior, Giovanni Ansaloni, David Atienza, Francisco J. Rincón, Srinivasan Murali
2013	A	`conf`	A methodology for embedded classification of heartbeats using random projections. DATE Rubén Braojos, Giovanni Ansaloni, David Atienza
2013	A	`conf`	Synchronizing code execution on ultra-low-power embedded multi-channel signal analysis platforms. DATE Ahmed Yasir Dogan, Rubén Braojos, Jeremy Constantin, Giovanni Ansaloni, Andreas Burg, David Atienza
2012	C	`conf`	Embedded real-time ECG delineation methods: A comparative evaluation. BIBE Rubén Braojos, Giovanni Ansaloni, David Atienza, Francisco J. Rincón
2012	C	`conf`	IcyHeart: Highly integrated ultra-low-power SoC solution for unobtrusive and energy efficient wireless cardiac monitoring: Research project for the benefit of specific groups (FP7, Capacities). BIBE Marios Milis, Kyriacos Michaelides, Anastasis Kounoudes, Giovanni Ansaloni, David Atienza, Frédéric Giroud, Pierre-François Ruedi, Frederic Masson
2012	J	`jnl`	Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Giovanni Ansaloni, Kazuyuki Tanimura, Laura Pozzi, Nikil D. Dutt
2011	J	`jnl`	EGRA: A Coarse Grained Reconfigurable Architectural Template. IEEE Trans. Very Large Scale Integr. Syst. Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi
2011	A	`conf`	Slack-aware scheduling on Coarse Grained Reconfigurable Arrays. DATE Giovanni Ansaloni, Laura Pozzi, Kazuyuki Tanimura, Nikil D. Dutt
2009	A	`conf`	Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration. DATE Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi
2008	Misc	`conf`	Compiling custom instructions onto expression-grained reconfigurable architectures. CASES Paolo Bonzini, Giovanni Ansaloni, Laura Pozzi
2008	—	`conf`	Design and Architectural Exploration of Expression-Grained Reconfigurable Arrays. SASP Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi