Giorgos Dimitrakopoulos

126 papers A* 2A 10B 2C 8Journal 62Unranked 39
YearRankTypeTitle / Venue / Authors
2026 J jnl
H-FA: A Hybrid Floating-Point and Logarithmic Approach to Hardware Accelerated FlashAttention.
IEEE Trans. Circuits Syst. Artif. Intell.
Kosmas Alexandridis, Giorgos Dimitrakopoulos
2026 J jnl
Vectorized FlashAttention with low-cost exponential computation in RISC-V vector processors.
J. Supercomput.
Vasileios Titopoulos, Kosmas Alexandridis, Giorgos Dimitrakopoulos
2025 — conf
Custom Algorithm-based Fault Tolerance for Attention Layers in Transformers.
SOCC
Vasileios Titopoulos, Kosmas Alexandridis, Giorgos Dimitrakopoulos
2025 J jnl
Custom Algorithm-based Fault Tolerance for Attention Layers in Transformers.
CoRR
Vasileios Titopoulos, Kosmas Alexandridis, Giorgos Dimitrakopoulos
2025 — conf
Efficient Implementation of RISC-V Vector Permutation Instructions.
ISVLSI
Vasileios Titopoulos, George Alexakis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2025 J jnl
Efficient Implementation of RISC-V Vector Permutation Instructions.
CoRR
Vasileios Titopoulos, George Alexakis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2025 A conf
FLASH-D: FlashAttention with Hidden Softmax Division.
ISLPED
Kosmas Alexandridis, Vasileios Titopoulos, Giorgos Dimitrakopoulos
2025 J jnl
FLASH-D: FlashAttention with Hidden Softmax Division.
CoRR
Kosmas Alexandridis, Vasileios Titopoulos, Giorgos Dimitrakopoulos
2025 J jnl
GCN-ABFT: Low-Cost Online Error Checking for Graph Convolutional Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Christodoulos Peltekis, Giorgos Dimitrakopoulos
2025 J jnl
H-FA: A Hybrid Floating-Point and Logarithmic Approach to Hardware Accelerated FlashAttention.
CoRR
Kosmas Alexandridis, Giorgos Dimitrakopoulos
2025 C conf
High-Performance Pipelined NTT Accelerators with Homogeneous Digit-Serial Modulo Arithmetic.
DSD
George Alexakis, Dimitrios Schoinianakis, Giorgos Dimitrakopoulos
2025 J jnl
High-Performance Pipelined NTT Accelerators with Homogeneous Digit-Serial Modulo Arithmetic.
CoRR
George Alexakis, Dimitrios Schoinianakis, Giorgos Dimitrakopoulos
2025 — conf
Low-Cost FlashAttention with Fused Exponential and Multiplication Hardware Operators.
ISVLSI
Kosmas Alexandridis, Vasileios Titopoulos, Giorgos Dimitrakopoulos
2025 J jnl
Low-Cost FlashAttention with Fused Exponential and Multiplication Hardware Operators.
CoRR
Kosmas Alexandridis, Vasileios Titopoulos, Giorgos Dimitrakopoulos
2025 J jnl
Online Alignment and Addition in Multiterm Floating-Point Adders.
IEEE Trans. Very Large Scale Integr. Syst.
Kosmas Alexandridis, Giorgos Dimitrakopoulos
2025 J jnl
Optimizing Structured-Sparse Matrix Multiplication in RISC-V Vector Processors.
CoRR
Vasileios Titopoulos, Kosmas Alexandridis, Christodoulos Peltekis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2025 J jnl
Optimizing Structured-Sparse Matrix Multiplication in RISC-V Vector Processors.
IEEE Trans. Computers
Vasileios Titopoulos, Kosmas Alexandridis, Christodoulos Peltekis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2025 — conf
Periodic Online Testing for Sparse Systolic Tensor Arrays.
MOCAST
Christodoulos Peltekis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2025 J jnl
Periodic Online Testing for Sparse Systolic Tensor Arrays.
CoRR
Christodoulos Peltekis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2025 — conf
Register Dispersion: Reducing the Footprint of the Vector Register File in Vector Engines of Low-Cost RISC-V CPUs.
CF
Vasileios Titopoulos, George Alexakis, Kosmas Alexandridis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2025 J jnl
Register Dispersion: Reducing the Footprint of the Vector Register File in Vector Engines of Low-Cost RISC-V CPUs.
CoRR
Vasileios Titopoulos, George Alexakis, Kosmas Alexandridis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2025 J jnl
Vectorized FlashAttention with Low-cost Exponential Computation in RISC-V Vector Processors.
CoRR
Vasileios Titopoulos, Kosmas Alexandridis, Giorgos Dimitrakopoulos
2024 J jnl
A High-Level Synthesis Library for Synthesizing Efficient and Functional-Safe CNN Dataflow Accelerators.
IEEE Access
Dionysios Filippas, Christodoulos Peltekis, Vasileios Titopoulos, Ioannis Kansizoglou, Georgios Ch. Sirakoulis, Antonios Gasteratos, Giorgos Dimitrakopoulos
2024 — conf
Comparative Analysis and Implementation of HTTP3, MQTT, and CoAP for IoT Applications.
PCI
Dimitris Koutras, Giorgos Dimitrakopoulos, Vangelis Malamas, Panayiotis Kotzanikolaou, Christos Douligeris
2024 J jnl
DeMM: A Decoupled Matrix Multiplication Engine Supporting Relaxed Structured Sparsity.
IEEE Comput. Archit. Lett.
Christodoulos Peltekis, Vasileios Titopoulos, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2024 J jnl
DeMM: A Decoupled Matrix Multiplication Engine Supporting Relaxed Structured Sparsity.
CoRR
Christodoulos Peltekis, Vasileios Titopoulos, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2024 — conf
Error Checking for Sparse Systolic Tensor Arrays.
AICAS
Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos
2024 J jnl
Error Checking for Sparse Systolic Tensor Arrays.
CoRR
Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos
2024 J jnl
Floating-Point Multiply-Add with Approximate Normalization for Low-Cost Matrix Engines.
CoRR
Kosmas Alexandridis, Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos
2024 J jnl
GCN-ABFT: Low-Cost Online Error Checking for Graph Convolutional Networks.
CoRR
Christodoulos Peltekis, Giorgos Dimitrakopoulos
2024 A conf
IndexMAC: A Custom RISC-V Vector Instruction to Accelerate Structured-Sparse Matrix Multiplications.
DATE
Vasileios Titopoulos, Kosmas Alexandridis, Christodoulos Peltekis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2024 J jnl
Online Alignment and Addition in Multi-Term Floating-Point Adders.
CoRR
Kosmas Alexandridis, Giorgos Dimitrakopoulos
2024 — conf
Reusing Softmax Hardware Unit for GELU Computation in Transformers.
AICAS
Christodoulos Peltekis, Kosmas Alexandridis, Giorgos Dimitrakopoulos
2024 J jnl
Reusing Softmax Hardware Unit for GELU Computation in Transformers.
CoRR
Christodoulos Peltekis, Kosmas Alexandridis, Giorgos Dimitrakopoulos
2023 A conf
ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining.
DATE
Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos, Dionisios N. Pnevmatikatos
2023 J jnl
Exploiting data encoding and reordering for low-power streaming in systolic arrays.
Microprocess. Microsystems
Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos
2023 J jnl
IndexMAC: A Custom RISC-V Vector Instruction to Accelerate Structured-Sparse Matrix Multiplications.
CoRR
Vasileios Titopoulos, Kosmas Alexandridis, Christodoulos Peltekis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2023 — conf
Low-Power Data Streaming in Systolic Arrays with Bus-Invert Coding and Zero-Value Clock Gating.
MOCAST
Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos
2023 J jnl
Low-Power Data Streaming in Systolic Arrays with Bus-Invert Coding and Zero-Value Clock Gating.
CoRR
Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos
2023 — conf
Multi-Armed Bandits for Autonomous Test Application in RISC-V Processor Verification.
MOCAST
Giorgos Dimitrakopoulos, E. Kallitsounakis, Z. Takakis, A. Stefanidis, Chrysostomos Nicopoulos
2023 — conf
Reduced-Precision Floating-Point Arithmetic in Systolic Arrays with Skewed Pipelines.
AICAS
Dionysios Filippas, Christodoulos Peltekis, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos
2023 J jnl
Reduced-Precision Floating-Point Arithmetic in Systolic Arrays with Skewed Pipelines.
CoRR
Dionysios Filippas, Christodoulos Peltekis, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos
2023 J jnl
Streaming Dilated Convolution Engine.
IEEE Trans. Very Large Scale Integr. Syst.
Dionysios Filippas, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2023 J jnl
Synthesis of Approximate Parallel-Prefix Adders.
IEEE Trans. Very Large Scale Integr. Syst.
Apostolos Stefanidis, Ioanna Zoumpoulidou, Dionysios Filippas, Giorgos Dimitrakopoulos, Georgios Ch. Sirakoulis
2023 J jnl
Task-Based Parallel Programming for Gate Sizing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Dimitrios Mangiras, David G. Chinnery, Giorgos Dimitrakopoulos
2023 J jnl
The Case for Asymmetric Systolic Array Floorplanning.
CoRR
Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos A. Nicopoulos
2022 J jnl
ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining.
CoRR
Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos, Dionisios N. Pnevmatikatos
2022 — conf
FusedGCN: A Systolic Three-Matrix Multiplication Architecture for Graph Convolutional Networks.
ASAP
Christodoulos Peltekis, Dionysios Filippas, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2022 A* conf
IDLD: Instantaneous Detection of Leakage and Duplication of Identifiers used for Register Renaming.
MICRO
Yiannakis Sazeides, Alex Gerber, Ron Gabor, Arkady Bramnik, George Papadimitriou, Dimitris Gizopoulos, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Karyofyllis Patsidis
2022 — conf
LeapConv: An Energy-Efficient Streaming Convolution Engine with Reconfigurable Stride.
ISVLSI
Dionysios Filippas, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2022 J jnl
Low-Cost Online Convolution Checksum Checker.
IEEE Trans. Very Large Scale Integr. Syst.
Dionysios Filippas, Nikolaos Margomenos, Nikolaos Mitianoudis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2022 — conf
Virtual-Channel Flow Control Across Mesochronous Clock Domains.
MOCAST
Giorgos Dimitrakopoulos, Anastasios Psarras, Chrysostomos Nicopoulos
2021 J jnl
Autonomous Application of Netlist Transformations Inside Lagrangian Relaxation-Based Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Apostolos Stefanidis, Dimitrios Mangiras, Chrysostomos Nicopoulos, David G. Chinnery, Giorgos Dimitrakopoulos
2021 — conf
Incremental Lagrangian Relaxation based Discrete Gate Sizing and Threshold Voltage Assignment.
MOCAST
Dimitrios Mangiras, Giorgos Dimitrakopoulos
2021 J jnl
Multicast-enabled network-on-chip routers leveraging partitioned allocation and switching.
Integr.
Dimitris Konstantinou, Chrysostomos Nicopoulos, Junghee Lee, Giorgos Dimitrakopoulos
2021 C conf
Sum Propagate Adders.
ARITH
Giorgos Dimitrakopoulos, Kleanthis Papachatzopoulos, Vassilis Paliouras
2021 J jnl
Sum Propagate Adders.
IEEE Trans. Emerg. Top. Comput.
Giorgos Dimitrakopoulos, Kleanthis Papachatzopoulos, Vassilis Paliouras
2020 — conf
2D Error Correction for F/F based Arrays using In-Situ Real-Time Error Detection (RTD).
DFT
Yiannakis Sazeides, Arkady Bramnik, Ron Gabor, Chrysostomos Nicopoulos, Ramon Canal, Dimitris Konstantinou, Giorgos Dimitrakopoulos
2020 — conf
Design Optimization by Fine-grained Interleaving of Local Netlist Transformations in Lagrangian Relaxation.
ISPD
Apostolos Stefanidis, Dimitrios Mangiras, Chrysostomos Nicopoulos, David G. Chinnery, Giorgos Dimitrakopoulos
2020 — conf
Memristive Learning Cellular Automata: Theory and Applications.
MOCAST
Rafailia-Eleni Karamani, Iosif-Angelos Fyrigos, Vasileios G. Ntinas, Orestis Liolis, Giorgos Dimitrakopoulos, Mustafa Altun, Andrew Adamatzky, Mircea R. Stan, Georgios Ch. Sirakoulis
2020 J jnl
Memristive Learning Cellular Automata: Theory and Applications.
CoRR
Rafailia-Eleni Karamani, Iosif-Angelos Fyrigos, Vasileios G. Ntinas, Orestis Liolis, Giorgos Dimitrakopoulos, Mustafa Altun, Andrew Adamatzky, Mircea R. Stan, Georgios Ch. Sirakoulis
2020 C conf
Memristive Oscillatory Circuits for Resolution of NP-Complete Logic Puzzles: Sudoku Case.
ISCAS
Theodoros Panagiotis Chatzinikolaou, Iosif-Angelos Fyrigos, Rafailia-Eleni Karamani, Vasileios G. Ntinas, Giorgos Dimitrakopoulos, Sorin Cotofana, Georgios Ch. Sirakoulis
2020 J jnl
Memristive oscillatory circuits for resolution of NP-complete logic puzzles: Sudoku case.
CoRR
Theodoros Panagiotis Chatzinikolaou, Iosif-Angelos Fyrigos, Rafailia-Eleni Karamani, Vasileios G. Ntinas, Giorgos Dimitrakopoulos, Sorin Cotofana, Georgios Ch. Sirakoulis
2020 C conf
RISC-V2: A Scalable RISC-V Vector Processor.
ISCAS
Karyofyllis Patsidis, Chrysostomos Nicopoulos, Georgios Ch. Sirakoulis, Giorgos Dimitrakopoulos
2020 C conf
SmartFork: Partitioned Multicast Allocation and Switching in Network-on-Chip Routers.
ISCAS
Dimitrios Konstantinou, Chrysostomos Nicopoulos, Junghee Lee, Georgios Ch. Sirakoulis, Giorgos Dimitrakopoulos
2020 — conf
Soft-Clustering Driven Flip-flop Placement Targeting Clock-induced OCV.
ISPD
Dimitrios Mangiras, Pavlos M. Mattheakis, Pierre-Olivier Ribet, Giorgos Dimitrakopoulos
2020 J jnl
The Mesochronous Dual-Clock FIFO Buffer.
IEEE Trans. Very Large Scale Integr. Syst.
Dimitrios Konstantinou, Anastasios Psarras, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2020 J jnl
Timing-Driven Placement Optimization Facilitated by Timing-Compatibility Flip-Flop Clustering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Dimitrios Mangiras, Apostolos Stefanidis, Ioannis Seitanidis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2019 J jnl
Automatic Generation of Peak-Power Traffic for Networks-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ioannis Seitanidis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2019 — conf
Dynamic Adjustment of Test-Sequence Duration for Increasing the Functional Coverage.
IVSW
Zacharias Takakis, Dimitrios Mangiras, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2019 A conf
Error-Shielded Register Renaming Sub-system for a Dynamically Scheduled Out-of-Order Core.
DATE
Ron Gabor, Yiannakis Sazeides, Arkady Bramnik, Alexandros Andreou, Chrysostomos Nicopoulos, Karyofyllis Patsidis, Dimitris Konstantinou, Giorgos Dimitrakopoulos
2019 — conf
Multi-Armed Bandits for Autonomous Timing-driven Design Optimization.
PATMOS
Apostolos Stefanidis, Dimitrios Mangiras, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2019 J jnl
Timing-Driven and Placement-Aware Multibit Register Composition.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ioannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David G. Chinnery
2018 J jnl
A low-cost synthesizable RISC-V dual-issue processor core leveraging the compressed Instruction Set Extension.
Microprocess. Microsystems
Karyofyllis Patsidis, Dimitris Konstantinou, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2018 — conf
Low-power dual-edge-triggered synchronous latency-insensitive systems.
MOCAST
Dimitris Konstantinou, Anastasios Psarras, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos
2017 J jnl
A Dual-Clock Multiple-Queue Shared Buffer.
IEEE Trans. Computers
Anastasios Psarras, Michalis Paschou, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2017 J jnl
Active Thermoelectric Cooling Solutions for Airspace Applications: the THERMICOOL Project.
IEEE Access
Emmanuel Karampasis, Nick P. Papanikolaou, Dionisis Voglitsis, Michael Loupis, Anastasios Psarras, Alexandros Boubaris, Dimitris Baros, Giorgos Dimitrakopoulos
2017 — conf
Low-cost congestion management in networks-on-chip using edge and in-network traffic throttling.
AISTECS@HiPEAC
Monobrata Debnath, Dimitris Konstantinou, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Wei-Ming Lin, Junghee Lee
2017 J jnl
Networks-on-Chip With Double-Data-Rate Links.
IEEE Trans. Circuits Syst. I Regul. Pap.
Anastasios Psarras, Savvas Moisidis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2017 A* conf
Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulation.
DAC
Ioannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David G. Chinnery
2016 — conf
A Low-Power Network-on-Chip Architecture for Tile-based Chip Multi-Processors.
ACM Great Lakes Symposium on VLSI
Anastasios Psarras, Junghee Lee, Pavlos M. Mattheakis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2016 J jnl
An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures.
ACM Trans. Archit. Code Optim.
Kypros Chrysanthou, Panayiotis Englezakis, Andreas Prodromou, Andreas Panteli, Chrysostomos Nicopoulos, Yiannakis Sazeides, Giorgos Dimitrakopoulos
2016 A conf
CrossOver: Clock domain crossing under virtual-channel flow control.
DATE
Michalis Paschou, Anastasios Psarras, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2016 J jnl
PhaseNoC: Versatile Network Traffic Isolation Through TDM-Scheduled Virtual Channels.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Anastasios Psarras, Junghee Lee, Ioannis Seitanidis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2016 — conf
Powermax: an automated methodology for generating peak-power traffic in networks-on-chip.
NOCS
Ioannis Seitanidis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2016 — ed.
Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC 2016, Prague, Czech Republic, January 18, 2016
AISTECS@HiPEAC
Sören Sonntag, Sandro Bartolini, Giorgos Dimitrakopoulos, José M. García
2016 — conf
RapidLink: A network-on-chip architecture with double-data-rate links.
ICECS
Anastasios Psarras, Savvas Moisidis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2016 J jnl
ShortPath: A Network-on-Chip Router with Fine-Grained Pipeline Bypassing.
IEEE Trans. Computers
Anastasios Psarras, Ioannis Seitanidis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2015 J jnl
ElastiStore: Flexible Elastic Buffering for Virtual-Channel-Based Networks on Chip.
IEEE Trans. Very Large Scale Integr. Syst.
Ioannis Seitanidis, Anastasios Psarras, Kypros Chrysanthou, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2015 A conf
PhaseNoC: TDM scheduling at the virtual-channel level for efficient network traffic isolation.
DATE
Anastasios Psarras, I. Seitanidis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2015 J jnl
The fast evolving landscape of on-chip communication - Selected future challenges and research avenues.
Des. Autom. Embed. Syst.
Davide Bertozzi, Giorgos Dimitrakopoulos, José Flich, Sören Sonntag
2015 C conf
Timing-resilient Network-on-Chip architectures.
IOLTS
Alexandros Panteloukas, Anastasios Psarras, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2014 J jnl
Editorial.
Des. Autom. Embed. Syst.
Davide Bertozzi, Giorgos Dimitrakopoulos, Sören Sonntag
2014 — conf
ElastiNoC: A self-testable distributed VC-based Network-on-Chip architecture.
NOCS
I. Seitanidis, Anastasios Psarras, Emmanouil Kalligeros, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2014 A conf
ElastiStore: An elastic buffer architecture for Network-on-Chip routers.
DATE
I. Seitanidis, Anastasios Psarras, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos
2014 A conf
Hardware primitives for the synthesis of multithreaded elastic systems.
DATE
Giorgos Dimitrakopoulos, I. Seitanidis, Anastasios Psarras, K. Tsiouris, Pavlos M. Mattheakis, Jordi Cortadella
2014 — ed.
Proceedings of the 2014 International Workshop on Network on Chip Architectures, NoCArc '14, Cambridge, United Kingdom, December 13-14, 2014
NoCArc@MICRO
Farhad Mehdipour, Giorgos Dimitrakopoulos
2014 — ed.
Proceedings of the 8th International Workshop on Interconnection Network Architecture - On-Chip, Multi-Chip, INA-OCMC 2014, Vienna, Austria, January 22, 2014
INA-OCMC@HiPEAC
Giorgos Dimitrakopoulos, Sören Sonntag, José Flich, Pascal Vivet
2013 J jnl
Merged Switch Allocation and Traversal in Network-on-Chip Switches.
IEEE Trans. Computers
Giorgos Dimitrakopoulos, Emmanouil Kalligeros, Costas Galanopoulos
2013 A conf
Switch folding: network-on-chip routers with time-multiplexed output ports.
DATE
Giorgos Dimitrakopoulos, N. Georgiadis, Chrysostomos Nicopoulos, Emmanouil Kalligeros
2012 B conf
DESA: Distributed Elastic Switch Architecture for efficient networks-on-FPGAS.
FPL
Antoni Roca, José Flich, Giorgos Dimitrakopoulos
2012 A conf
Dynamic-priority arbiter and multiplexer soft macros for on-chip networks switches.
DATE
Giorgos Dimitrakopoulos, Emmanouil Kalligeros
2012 J jnl
LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors.
IEEE Trans. Very Large Scale Integr. Syst.
Darío Suárez Gracia, Giorgos Dimitrakopoulos, Teresa Monreal Arnal, Manolis Katevenis, Víctor Viñals Yúfera
2012 — conf
Low-cost fault-tolerant switch allocator for network-on-chip routers.
INA-OCMC@HiPEAC
Giorgos Dimitrakopoulos, Emmanouil Kalligeros
2012 J jnl
On Modulo 2^n+1 Adder Design.
IEEE Trans. Computers
Haridimos T. Vergos, Giorgos Dimitrakopoulos
2011 B conf
Scalable Arbiters and Multiplexers for On-FGPA Interconnection Networks.
FPL
Giorgos Dimitrakopoulos, Christoforos Kachris, Emmanouil Kalligeros
2011 — conf
Switch allocator for bufferless network-on-chip routers.
INA-OCMC@HiPEAC
Giorgos Dimitrakopoulos, Kostas Galanopoulos
2009 J jnl
A management scheme for improving transportation efficiency and contributing to the enhancement of the social fabric.
Telematics Informatics
Yiouli Kritikou, Giorgos Dimitrakopoulos, E. Dimitrellou, Panagiotis Demestichas
2009 J jnl
Practical High-Throughput Crossbar Scheduling.
IEEE Micro
Nikos Chrysos, Giorgos Dimitrakopoulos
2008 — conf
Backlog-Aware Crossbar Schedulers: A New Algorithm and its Efficient Hardware Implementation.
Hot Interconnects
Nikos Chrysos, Giorgos Dimitrakopoulos
2008 C conf
Fast arbiters for on-chip network switches.
ICCD
Giorgos Dimitrakopoulos, Nikos Chrysos, Costas Galanopoulos
2008 J jnl
Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units.
IEEE Trans. Very Large Scale Integr. Syst.
Giorgos Dimitrakopoulos, Costas Galanopoulos, Christos Mavrokefalidis, Dimitris Nikolos
2007 J jnl
Sorter Based Permutation Units for Media-Enhanced Microprocessors.
IEEE Trans. Very Large Scale Integr. Syst.
Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos
2006 — conf
An Energy-Delay Efficient Subword Permutation Unit.
ASAP
Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos
2006 C conf
Fast bit permutation unit for media enhanced microprocessors.
ISCAS
Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos
2005 — conf
Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing.
PATMOS
Giorgos Dimitrakopoulos, Dimitris Nikolos
2005 J jnl
Efficient Diminished-1 Modulo 2^n+1 Multipliers.
IEEE Trans. Computers
Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos
2005 J jnl
High-Speed Parallel-Prefix VLSI Ling Adders.
IEEE Trans. Computers
Giorgos Dimitrakopoulos, Dimitris Nikolos
2005 — conf
New architectures for modulo 2N - 1 adders.
ICECS
Giorgos Dimitrakopoulos, Dimitris G. Nikolos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
2004 J jnl
A novel architecture and a systematic graph-based optimization methodology for modulo multiplication.
IEEE Trans. Circuits Syst. I Regul. Pap.
Giorgos Dimitrakopoulos, Vassilis Paliouras
2004 — conf
Design of High-Speed Low-Power Parallel-Prefix VLSI Adders.
PATMOS
Giorgos Dimitrakopoulos, Pavlos Kolovos, P. Kalogerakis, Dimitris Nikolos
2003 — conf
A Family of Parallel-Pre.x Modulo 2n - 1 Adders.
ASAP
Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
2003 — conf
A systematic methodology for designing area-time efficient parallel-prefix modulo 2
ISCAS (5)
Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
2003 — conf
Efficient modulo 2
ICECS
Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos
2003 — conf
Virtual-scan: a novel approach for software-based self-testing of microprocessors.
ISCAS (5)
Giorgos Dimitrakopoulos, Xrysovalantis Kavousianos, Dimitris Nikolos
2002 — conf
Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register.
IOLTW
Giorgos Dimitrakopoulos, Dimitris Nikolos, Dimitris Bakalis