Ginés Doménech-Asensi

37 papers A 2B 2C 9Journal 12Unranked 12

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	An Efficient-Energy Charge-Domain Convolution Operator for CNN. IEEE Access José Ángel Díaz-Madrid, Ginés Doménech-Asensi, Ramón Ruiz Merino, Francisco Javier Andreo-Oliver
2025	C	`conf`	Interlaced 6T-10T CMOS in-memory computing circuit for low silicon area pipelined DNNs. ISCAS Ginés Doménech-Asensi, Francisco Javier Andreo-Oliver, Ramón Ruiz Merino, José Ángel Díaz-Madrid
2024	J	`jnl`	A real-time and energy-efficient SRAM with mixed-signal in-memory computing near CMOS sensors. J. Real Time Image Process. José Ángel Díaz-Madrid, Ginés Doménech-Asensi, Ramón Ruiz Merino, Juan Zapata-Pérez
2024	J	`jnl`	Accelerated Simulation of Passive Analog Circuits Over GPU Using Explicit Integration Methods. Circuits Syst. Signal Process. Ginés Doménech-Asensi, Tom J. Kazmierski
2023	C	`conf`	A 12T SRAM in-Memory Computing differential current architecture for CNN implementations. ISCAS Ginés Doménech-Asensi, Ramón Ruiz Merino, Juan Zapata-Pérez, José Ángel Díaz-Madrid
2022	J	`jnl`	On the Use of Bayesian Networks for Real-Time Urban Traffic Measurements: a Case Study with Low-Cost Devices. J. Signal Process. Syst. Ginés Doménech-Asensi, María-Dolores Cano, Víctor Morales-Esteras
2021	—	`conf`	A library-based tool to translate high level DNN models into hierarchical VHDL descriptions. DCIS Pablo Rubio-Ibáñez, J. Javier Martínez-Álvarez, Ginés Doménech-Asensi
2021	J	`jnl`	Joint Implementation of the Sharing OTA and Bias Current Regulation Techniques in an 11-Bit 10 MS/s Pipelined ADC. Circuits Syst. Signal Process. José Ángel Díaz-Madrid, Ginés Doménech-Asensi, J. Javier Martínez-Álvarez, Juan Zapata-Pérez, Ramón Ruiz Merino
2020	J	`jnl`	All-hardware SIFT implementation for real-time VGA images feature extraction. J. Real Time Image Process. Ginés Doménech-Asensi, Juan Zapata-Pérez, Ramón Ruiz Merino, José-Alejandro López Alcantud, José Ángel Díaz-Madrid, Víctor Manuel Brea Sánchez, Paula López
2020	A	`conf`	High-speed analog simulation of CMOS vision chips using explicit integration techniques on many-core processors. DATE Ginés Doménech-Asensi, Tom J. Kazmierski
2020	C	`conf`	Mixed Signal Multiply and Adder Parallel Circuit for Deep Learning Convolution Operations. ISCAS José Ángel Díaz-Madrid, Ginés Doménech-Asensi, Ramón Ruiz Merino, Juan Zapata-Pérez, José Javier Martínez
2020	C	`conf`	Stability and Efficiency of Explicit Integration in Interconnect Analysis on GPUs. ISCAS Ginés Doménech-Asensi, Tom J. Kazmierski
2019	C	`conf`	An Efficient Numerical Solution Technique for VLSI Interconnect Equations on Many-Core Processors. ISCAS Ginés Doménech-Asensi, Tom J. Kazmierski
2019	C	`conf`	Efficient VHDL Implementation of an Upscaling Function for Real Time Video Applications. ISCAS Pablo Rubio-Ibáñez, J. Javier Martínez-Álvarez, Ginés Doménech-Asensi
2019	C	`conf`	Simulation Acceleration of Image Filtering on CMOS Vision Chips Using Many-Core Processors. FDL Ginés Doménech-Asensi, Tom J. Kazmierski
2018	J	`jnl`	An all-hardware implementation of the subpixel refinement stage in SIFT algorithm. Int. J. Circuit Theory Appl. Pablo Rubio-Ibáñez, Ramón Ruiz Merino, Ginés Doménech-Asensi, J. Javier Martínez-Álvarez, Juan Zapata-Pérez, José Ángel Díaz-Madrid, José-Alejandro López Alcantud
2018	—	`conf`	FPGA real time synthesis of simplified SIFT algorithm. ICDSC Pablo Rubio-Ibáñez, J. Javier Martínez-Álvarez, Ginés Doménech-Asensi
2018	—	`conf`	Results of 'iCaveats', a Project on the Integration of Architectures and Components for Embedded Vision. ICDSC Ricardo Carmona-Galán, Jorge Fernández-Berni, Ángel Rodríguez-Vázquez, Paula López Martinez, Víctor Manuel Brea Sánchez, Diego Cabello Ferrer, Ginés Doménech-Asensi, Ramón Ruiz Merino, Juan Zapata-Pérez
2018	—	`conf`	Traffic Metrics at Urban Intersections using a Low-Cost Image Processing Approach. ICDSC Juan Francisco Inglés-Romero, Ginés Doménech-Asensi, María-Dolores Cano-Baños, Víctor Morales-Esteras
2017	C	`conf`	An 11-bit 20-MSample/s pipelined ADC with OTA bias current regulation to optimize power dissipation. ISCAS José Ángel Díaz-Madrid, Ginés Doménech-Asensi, José-Alejandro López Alcantud, M. Oberst
2017	—	`conf`	Generation of new power processing structures exploiting genetic programming. ISIE Ginés Doménech-Asensi, Tom J. Kazmierski
2016	—	`conf`	Proactive Intelligent System for Optimizing Traffic Signaling. DASC/PiCom/DataCom/CyberSciTech Ramon Sanchez-Iborra, Juan F. Inglés-Romero, Ginés Doménech-Asensi, José-Luis Moreno-Cegarra, María-Dolores Cano
2015	J	`jnl`	Distance Measurement Error in Time-of-Flight Sensors Due to Shot Noise. Sensors Julio Illade-Quinteiro, Víctor M. Brea, Paula López Martinez, Diego Cabello, Ginés Doménech-Asensi
2014	B	`conf`	Simplification and hardware implementation of the feature descriptor vector calculation in the SIFT algorithm. FPL Pablo Leyva, Ginés Doménech-Asensi, F. Javier Garrigós, Julio Illade-Quinteiro, Víctor M. Brea, Paula López, Diego Cabello
2013	J	`jnl`	Synthesis of CMOS analog circuit VHDL-AMS descriptions using parameterizable macromodels. Int. J. Circuit Theory Appl. Ginés Doménech-Asensi, José Ángel Díaz-Madrid, Ramón Ruiz Merino
2013	—	`conf`	Voltage boosters for on-chip solar cells on focal-plane processors. ICECS Víctor M. Brea, Manuel Suarez, J. Illade-Quinteiro, Paula López, Diego Cabello, Ginés Doménech-Asensi
2012	—	`conf`	A fourth order CMOS band pass filter for PIR sensors. ICECS Ginés Doménech-Asensi, F. Martinez-Viviente, J. Illade-Quinteiro, Juan Zapata-Pérez, Ramón Ruiz Merino, José-Alejandro López Alcantud, Juan Martínez-Alajarín, Francisco J. Fernández-Luque, Juan M. Carrillo, Miguel Angel Domínguez
2011	J	`jnl`	A secure energy-efficient m-banking application for mobile devices. J. Syst. Softw. María-Dolores Cano, Ginés Doménech-Asensi
2010	J	`jnl`	Fuzzy logic technique for accurate analog circuits macromodel sizing. Int. J. Circuit Theory Appl. José Ángel Díaz-Madrid, Juan Hinojosa, Ginés Doménech-Asensi
2009	A	`conf`	Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing. DATE José Ángel Díaz-Madrid, Harald Neubauer, Hans Hauer, Ginés Doménech-Asensi, Ramón Ruiz Merino
2008	C	`conf`	Accurate and reusable macromodeling technique using a fuzzy-logic approach. ISCAS Ginés Doménech-Asensi, Juan Hinojosa, Ramón Ruiz Merino, José Ángel Díaz-Madrid
2007	J	`jnl`	A behavioral model development methodology for microwave components and integration in VHDL-AMS. Microelectron. J. Ginés Doménech-Asensi, Juan Hinojosa, Juan Martínez-Alajarín
2007	—	`conf`	Improvement of ANNs Performance to Generate Fitting Surfaces for Analog CMOS Circuits. IWINAC (2) José Ángel Díaz-Madrid, Pedro Monsalve-Campillo, Juan Hinojosa, María Victoria Rodellar Biarge, Ginés Doménech-Asensi
2007	—	`conf`	Multiple adaptive neuro-fuzzy inference systems for accurate microwave CAD applications. ECCTD Juan Hinojosa, Ginés Doménech-Asensi
2006	B	`conf`	Synthesis on FPAA of a Smart Sthetoscope Analog Subsystem. FPL Ginés Doménech-Asensi, Juan Martínez-Alajarín, Ramón Ruiz Merino, José-Alejandro López Alcantud
2005	—	`conf`	Description and Simulation of Bio-inspired Systems Using VHDL-AMS. IWINAC (2) Ginés Doménech-Asensi, José-Alejandro López Alcantud, Ramón Ruiz Merino
2003	—	`conf`	Current Mode CMOS Synthesis of a Motor-Control Neural System. IWANN (2) Ginés Doménech-Asensi, Ramón Ruiz Merino, Hans Hauer, José Ángel Díaz-Madrid