Gil-Cho Ahn

46 papers C 3Journal 20Unranked 23
YearRankTypeTitle / Venue / Authors
2026 J jnl
A Hybrid Voltage-Time Domain Pipelined ADC With Reference-Embedded Time-Domain Residues.
IEEE J. Solid State Circuits
Jae-Geun Lim, Jun-Ho Boo, Jae-Hyuk Lee, Hyoung-Jung Kim, Byeongho Yu, Kang-Il Cho, Sungho Lee, Un-Ku Moon, Gil-Cho Ahn
2025 — conf
A Two-Step ADC with a Separate DAC Method for Enhanced Sub-Quantizer Settling Condition.
ICEIC
Jae-Geun Lim, Jun-Ho Boo, Hyoung-Jung Kim, Jae-Hyuk Lee, Kang-Il Cho, Gil-Cho Ahn
2024 — conf
A CMOS Analog Front-End for Hall Sensor Readout IC.
ICEIC
Kang-Il Cho, Jun-Ho Boo, Jae-Geun Lim, Gil-Cho Ahn
2023 — conf
A 12-bit 3-MS/s Synchronous SAR ADC With a Hybrid RC DAC.
ISOCC
Mi-Ji Go, Jun-Ho Boo, Jae-Geun Lim, Hyoung-Jung Kim, Jae-Hyuk Lee, Seong-Bo Park, Byeongho Yu, Won-Jun Cho, Gil-Cho Ahn
2023 — conf
A Second-Order DT Delta-Sigma Modulator with Noise-Shaping SAR Quantizer.
ISOCC
Seong-Bo Park, Jun-Ho Boo, Jae-Geun Lim, Hyoung-Jung Kim, Jae-Hyuk Lee, Won-Jun Cho, Gil-Cho Ahn
2023 J jnl
A Single-Loop Third-Order 10-MHz BW Source-Follower-Integrator Based Discrete-Time Delta-Sigma ADC.
IEEE Trans. Circuits Syst. II Express Briefs
Ho-Jin Kim, Jun-Ho Boo, Kang-Il Cho, Yong-Sik Kwak, Gil-Cho Ahn
2022 — conf
A 430-MS/s 7-b Asynchronous SAR ADC With a 40 fF Input Sampling Capacitor.
ISOCC
Hyoung-Jung Kim, Jae-Hyuk Lee, Jae-Geun Lim, Jun-Ho Boo, Ho-Jin Kim, Seong-Bo Park, Youngdon Choi, Jung-Hwan Choi, Gil-Cho Ahn
2021 — conf
A 0.9V 0.022mm
A-SSCC
Yong-Sik Kwak, Ho-Jin Kim, Kang-Il Cho, Jun-Ho Boo, Gil-Cho Ahn
2021 J jnl
A 96dB Dynamic Range 2kHz Bandwidth 2nd Order Delta-Sigma Modulator Using Modified Feed-Forward Architecture With Delayed Feedback.
IEEE Trans. Circuits Syst. II Express Briefs
Ju-Hye Han, Kang-Il Cho, Ho-Jin Kim, Jun-Ho Boo, Jae Sang Kim, Gil-Cho Ahn
2021 J jnl
A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3σ Inaccuracy of +0.02%, -0.12% for Battery-Monitoring Applications.
IEEE J. Solid State Circuits
Jun-Ho Boo, Kang-Il Cho, Ho-Jin Kim, Jae-Geun Lim, Yong-Sik Kwak, Seung-Hoon Lee, Gil-Cho Ahn
2020 — conf
A 10-b 900-MS/s Single-Channel Pipelined-SAR ADC Using Current-Mode Reference Scaling.
A-SSCC
Kang-Il Cho, Ho-Jin Kim, Jun-Ho Boo, Yong-Sik Kwak, Jun-Sang Park, Seung-Hoon Lee, Gil-Cho Ahn
2020 — conf
A 2.2mW 12-bit 200MS/s 28nm CMOS Pipelined SAR ADC with Dynamic Register-Based High-Speed SAR Logic.
A-SSCC
Jun-Sang Park, Je-Min Jeon, Jun-Ho Boo, Jae-Hyuk Lee, Kang-Il Cho, Ho-Jin Kim, Gil-Cho Ahn, Seung-Hoon Lee
2020 — conf
A Single-Trim Switched Capacitor CMOS Bandgap Reference with a 3σ Inaccuracy of +0.02%, -0.12% for Battery Monitoring Applications.
VLSI Circuits
Jun-Ho Boo, Kang-Il Cho, Ho-Jin Kim, Jae-Geun Lim, Yong-Sik Kwak, Seung-Hoon Lee, Gil-Cho Ahn
2020 — conf
A Third-Order DT Delta-Sigma Modulator With Noise-Coupling Technique.
ISOCC
Tae-Gwan Kim, Kang-Il Cho, Ho-Jin Kim, Jun-Ho Boo, Yong-Sik Kwak, Gil-Cho Ahn
2019 — conf
A 10-b 320-MS/s Dual-Residue Pipelined SAR ADC with Binary Search Current Interpolator.
CICC
Kang-Il Cho, Yong-Sik Kwak, Ho-Jin Kim, Jun-Ho Boo, Seung-Hoon Lee, Gil-Cho Ahn
2019 — conf
A 101 dB Dynamic Range Delta-Sigma Modulator Using Modified Feed-Forward Architecture for Audio Application.
ISOCC
Jun-Young Kil, Kang-Il Cho, Ho-Jin Kim, Jun-Ho Boo, Yong-Sik Kwak, Gil-Cho Ahn
2019 J jnl
A 12.1 fJ/Conv.-Step 12b 140 MS/s 28-nm CMOS Pipelined SAR ADC Based on Energy-Efficient Switching and Shared Ring Amplifier.
IEEE Trans. Circuits Syst. II Express Briefs
Jun-Sang Park, Tai-Ji An, Gil-Cho Ahn, Seung-Hoon Lee
2018 J jnl
A 101 dB dynamic range, 2 kHz bandwidth delta-sigma modulator with a modified feed-forward architecture.
IEICE Electron. Express
Kang-Il Cho, Yong-Sik Kwak, Ho-Jin Kim, Gil-Cho Ahn
2018 J jnl
A 72.9-dB SNDR 20-MHz BW 2-2 Discrete-Time Resolution-Enhanced Sturdy MASH Delta-Sigma Modulator Using Source-Follower-Based Integrators.
IEEE J. Solid State Circuits
Yong-Sik Kwak, Kang-Il Cho, Ho-Jin Kim, Seung-Hoon Lee, Gil-Cho Ahn
2018 J jnl
Area-Efficient Time-Shared Digital-to-Analog Converter With Dual Sampling for AMOLED Column Driver IC's.
IEEE Trans. Circuits Syst. I Regul. Pap.
Tai-Ji An, Moon-Sang Hwang, Won-Jun Choe, Gil-Cho Ahn, Seung-Hoon Lee
2018 J jnl
Two CMOS time to digital converters using successive approximation register logic.
IEICE Electron. Express
Himchan Park, Qiwei Huang, Changzhi Yu, Seulki Kim, Gil-Cho Ahn, Jinwook Burm
2017 J jnl
A 1.8 V 89.2 dB dynamic range delta-sigma modulator using an op-amp dynamic current biasing technique.
IEICE Electron. Express
Yong-Sik Kwak, Kang-Il Cho, Ho-Jin Kim, Gil-Cho Ahn
2017 — conf
A 72.9-dB SNDR 20-MHz BW 2-2 discrete-time sturdy MASH delta-sigma modulator using source-follower-based integrators.
A-SSCC
Yong-Sik Kwak, Kang-Il Cho, Ho-Jin Kim, Seung-Hoon Lee, Gil-Cho Ahn
2017 — conf
Analog front-end for EMG acquisition system.
ISOCC
Bum-Sik Chung, Hyeong-Kyu Kim, Kang-Il Cho, Ho-Jin Kim, Gil-Cho Ahn
2014 — conf
A 12-bit 200-kS/s SAR ADC with hybrid RC DAC.
APCCAS
Mi-rim Kim, Young-Ouk Kim, Yong-Sik Kwak, Gil-Cho Ahn
2013 C conf
10b 150MS/s 0.4mm
ISCAS
Tai-Ji An, Jun-Sang Park, Yongmin Kim, Suk-Hee Cho, Gil-Cho Ahn, Seung-Hoon Lee
2012 — conf
A 1.1 V 82.3dB audio ΔΣ ADC using asynchronous SAR type quantizer.
ICECS
Youngmin Park, Tae-In Kwon, Kang-Il Cho, Yong-Sik Kwak, Gil-Cho Ahn, Chang-Seob Shin, Myung-Jin Lee, Seung-Bin You, Ho-Jin Park
2012 C conf
A 1.8 V 89.2 dB delta-sigma adc for sensor interface with on-chip reference.
ISCAS
Yong-Sik Kwak, Kwang-Soo Kim, Gil-Cho Ahn
2012 — conf
A 10b 1MS/s-to-10MS/s 0.11um CMOS SAR ADC for analog TV applications.
ISOCC
Sang-Pil Nam, Yongmin Kim, Dong-Hyun Hwang, Hyo-Jin Kim, Tai-Ji An, Jun-Sang Park, Suk-Hee Cho, Gil-Cho Ahn, Seung-Hoon Lee
2012 — conf
A digitally enhanced low-distortion delta-sigma modulator for wideband application.
ISOCC
Jae-Hyeon Shin, Kang-Il Cho, Gil-Cho Ahn
2011 J jnl
A 10-bit 100-MS/s Dual-Channel Pipelined ADC Using Dynamic Memory Effect Cancellation Technique.
IEEE Trans. Circuits Syst. II Express Briefs
Chang-Seob Shin, Gil-Cho Ahn
2011 J jnl
A 14b 150 MS/s 140 mW 2.0 mm
Int. J. Circuit Theory Appl.
Hee-Cheol Choi, Pil-Seon Yoo, Gil-Cho Ahn, Seung-Hoon Lee
2011 C conf
A 6.25 MHz BW 8-OSR fifth-order single-stage sigma-delta ADC.
ISCAS
Chang-Seob Shin, Min-Ho Yoon, Kang-Il Cho, Young-Ju Kim, Kwang-Soo Kim, Seung-Hoon Lee, Gil-Cho Ahn
2011 J jnl
A Single Amplifier-Based 12-bit 100 MS/s 1 V 19 mW 0.13 µm CMOS ADC with Various Power and Area Minimized Circuit Techniques.
IEICE Trans. Electron.
Byeong-Woo Koo, Seung-Jae Park, Gil-Cho Ahn, Seung-Hoon Lee
2011 — conf
A ΔΣ ADC using 4-bit SAR type quantizer for audio applications.
ISOCC
Jin-Seon Kim, Tae-In Kwon, Gil-Cho Ahn, Yi-Gyeong Kim, Jong-Kee Kwon
2010 — conf
A 10mW stereo audio CODEC in 0.13µm CMOS.
ISSCC
Xicheng Jiang, Jungwoo Song, Todd Brooks, Jianlong Chen, Vinay Chandrasekhar, Felix Cheung, Sherif Galal, Darwin Cheung, Gil-Cho Ahn, Madhulatha Bonu
2010 J jnl
A 12 bit 50 MS/s CMOS Nyquist A/D Converter With a Fully Differential Class-AB Switched Op-Amp.
IEEE J. Solid State Circuits
Young-Ju Kim, Hee-Cheol Choi, Gil-Cho Ahn, Seung-Hoon Lee
2009 J jnl
A 1.2-V 12-b 120-MS/s SHA-Free Dual-Channel Nyquist ADC Based on Midcode Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap.
Seung-Hoon Lee, Young-Ju Kim, Hee-Cheol Choi, Gil-Cho Ahn
2009 — conf
A 9.43-ENOB 160MS/s 1.2V 65nm CMOS ADC based on multi-stage amplifiers.
CICC
Young-Ju Kim, Hee-Cheol Choi, Kyung-Hoon Lee, Gil-Cho Ahn, Seung-Hoon Lee, Ju-Hwa Kim, Kyoung-Jun Moon, Michael Choi, Kyoung-Ho Moon, Ho-Jin Park, Byeong-Ha Park
2008 J jnl
A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC.
IEEE J. Solid State Circuits
Min-Gyu Kim, Gil-Cho Ahn, Pavan Kumar Hanumolu, Sanghyeon Lee, Sang-Ho Kim, Seung-Bin You, Jae-Whui Kim, Gabor C. Temes, Un-Ku Moon
2007 — conf
A 1V 10b 30MSPS Switched-RC Pipelined ADC.
CICC
Gil-Cho Ahn, Min-Gyu Kim, Pavan Kumar Hanumolu, Un-Ku Moon
2005 J jnl
A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators.
IEEE J. Solid State Circuits
Gil-Cho Ahn, Dong-Young Chang, Matthew E. Brown, Naoto Ozaki, Hiroshi Youra, Ken Yamamura, Koichi Hamashita, Kaoru Takasuka, Gábor C. Temes, Un-Ku Moon
2005 J jnl
A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR.
IEEE J. Solid State Circuits
Jipeng Li, Gil-Cho Ahn, Dong-Young Chang, Un-Ku Moon
2005 J jnl
Sub-1-V design techniques for high-linearity multistage/pipelined analog-to-digital converters.
IEEE Trans. Circuits Syst. I Regul. Pap.
Dong-Young Chang, Gil-Cho Ahn, Un-Ku Moon
2004 — conf
An improved algorithmic ADC clocking scheme.
ISCAS (1)
Min-Gyu Kim, Gil-Cho Ahn, Un-Ku Moon
1996 J jnl
A 12-b, 10-MHz, 250-mW CMOS A/D converter.
IEEE J. Solid State Circuits
Gil-Cho Ahn, Hee-Cheol Choi, Shin-Il Lim, Seung-Hoon Lee, Chul-Dong Lee