Gianluca Piccinini

54 papers A* 1A 4B 1C 1Misc 2Journal 24Unranked 20

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Technology and Power-aware Investigation of Nanostructures for Molecular Field-Coupled Nanocomputing. ISVLSI Elena Ferrero, Federico Ravera, Roberto Listo, Yuri Ardesi, Gianluca Piccinini, Mariagrazia Graziano
2023	J	`jnl`	Advances in Modeling of Noisy Quantum Computers: Spin Qubits in Semiconductor Quantum Dots. IEEE Access Davide Costa, Mario Simoni, Gianluca Piccinini, Mariagrazia Graziano
2023	J	`jnl`	Design of Pyrrole-Based Gate-Controlled Molecular Junctions Optimized for Single-Molecule Aflatoxin B1 Detection. Sensors Fabrizio Mo, Chiara Elfi Spano, Yuri Ardesi, Massimo Ruo Roch, Gianluca Piccinini, Mariagrazia Graziano
2023	J	`jnl`	Taming Molecular Field-Coupling for Nanocomputing Design. ACM J. Emerg. Technol. Comput. Syst. Yuri Ardesi, Umberto Garlando, Fabrizio Riente, Giuliana Beretta, Gianluca Piccinini, Mariagrazia Graziano
2021	—	`conf`	A Reconfigurable Field-Coupled Nanocomputing Paradigm on Uniform Molecular Monolayers. ICRC Yuri Ardesi, Giuliana Beretta, Christian Fabiano, Mariagrazia Graziano, Gianluca Piccinini
2021	J	`jnl`	SCERPA Simulation of Clocked Molecular Field-Coupling Nanocomputing. IEEE Trans. Very Large Scale Integr. Syst. Yuri Ardesi, Giovanna Turvani, Mariagrazia Graziano, Gianluca Piccinini
2020	J	`jnl`	SCERPA: A Self-Consistent Algorithm for the Evaluation of the Information Propagation in Molecular Field-Coupled Nanocomputing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yuri Ardesi, Ruiyu Wang, Giovanna Turvani, Gianluca Piccinini, Mariagrazia Graziano
2019	—	`conf`	Bistable Propagation of Monostable Molecules in Molecular Field-Coupled Nanocomputing. PRIME Yuri Ardesi, Luca Gnoli, Mariagrazia Graziano, Gianluca Piccinini
2018	J	`jnl`	Nanoarrays for Systolic Biosequence Analysis. J. Circuits Syst. Comput. Malik Ashter Mehdy, Aleandro Antidormi, Mariagrazia Graziano, Gianluca Piccinini
2015	J	`jnl`	Process Variability and Electrostatic Analysis of Molecular QCA. ACM J. Emerg. Technol. Comput. Syst. Mariagrazia Graziano, Azzurra Pulimeno, Ruiyu Wang, Xiang Wei, Massimo Ruo Roch, Gianluca Piccinini
2015	J	`jnl`	Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT. IEEE Trans. Circuits Syst. I Regul. Pap. Maurizio Martina, Guido Masera, Massimo Ruo Roch, Gianluca Piccinini
2014	J	`jnl`	A Parallel Radix-Sort-Based VLSI Architecture for Finding the First W Maximum/Minimum Values. IEEE Trans. Circuits Syst. II Express Briefs Guoping Xiao, Maurizio Martina, Guido Masera, Gianluca Piccinini
2014	—	`conf`	Molecular transistor circuits: From device model to circuit simulation. NANOARCH Ali Zahir, Syed Azhar Ali Zaidi, Azzurra Pulimeno, Mariagrazia Graziano, Danilo Demarchi, Guido Masera, Gianluca Piccinini
2014	—	`ch.`	Understanding a Bisferrocene Molecular QCA Wire. Field-Coupled Nanocomputing Azzurra Pulimeno, Mariagrazia Graziano, Aleandro Antidormi, Ruiyu Wang, Ali Zahir, Gianluca Piccinini
2014	J	`jnl`	Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced. IEEE Signal Process. Lett. Carlo Condo, Maurizio Martina, Gianluca Piccinini, Guido Masera
2013	—	`conf`	Charge distribution in a molecular QCA wire based on bis-ferrocene molecules. NANOARCH Azzurra Pulimeno, Mariagrazia Graziano, Ruiyu Wang, Danilo Demarchi, Gianluca Piccinini
2013	—	`conf`	Nanogap-based enzymatic-free electrochemical detection of glucose. BioCAS Ismael Rattalino, Paolo Motto Ros, Irene Taurino, Fernando Cortes-Salazar, Gianluca Piccinini, Danilo Demarchi, Giovanni De Micheli, Sandro Carrara
2012	J	`jnl`	UDSM Trends Comparison: From Technology Roadmap to UltraSparc Niagara2. IEEE Trans. Very Large Scale Integr. Syst. Azzurra Pulimeno, Mariagrazia Graziano, Gianluca Piccinini
2010	J	`jnl`	Scalable low-complexity B-spline discrete wavelet transform architecture. IET Circuits Devices Syst. Maurizio Martina, Guido Masera, Gianluca Piccinini
2008	J	`jnl`	Statistical power supply dynamic noise prediction in hierarchical power grid and package networks. Integr. Mariagrazia Graziano, Gianluca Piccinini
2004	J	`jnl`	An electromigration and thermal model of power wires for a priori high-level reliability prediction. IEEE Trans. Very Large Scale Integr. Syst. Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
2004	J	`jnl`	Effects of temperature in deep-submicron global interconnect optimization in future technology nodes. Microelectron. J. Mariagrazia Graziano, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
2003	—	`conf`	A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization. PATMOS M. Addino, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
2003	J	`jnl`	Coupled electro-thermal modeling and optimization of clock networks. Microelectron. J. Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
2003	—	`conf`	Effects of Temperature in Deep-Submicron Global Interconnect Optimization. PATMOS Mario R. Casu, Mariagrazia Graziano, Gianluca Piccinini, Guido Masera, Maurizio Zamboni
2003	J	`jnl`	Novel JPEG 2000 Compliant DWT and IWT VLSI Implementations. J. VLSI Signal Process. Maurizio Martina, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
2003	A	`conf`	Wireless sensor networks: a power-scalable motion estimation IP for hybrid video coding. FPGA Federico Quaglio, Maurizio Martina, Fabrizio Vacca, Guido Masera, Andrea Molino, Gianluca Piccinini, Maurizio Zamboni
2002	J	`jnl`	Architectural strategies for low-power VLSI turbo decoders. IEEE Trans. Very Large Scale Integr. Syst. Guido Masera, Marco Mazza, Gianluca Piccinini, Fabrizio Viglione, Maurizio Zamboni
2002	—	`conf`	Clock Distribution Network Optimization under Self-Heating and Timing Constraints. PATMOS Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, M. M. Prono, Maurizio Zamboni
2002	—	`conf`	Embedded IWT evaluation in reconfigurable wireless sensor network. ICECS Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni
2002	B	`conf`	Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor. FPL Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni
2002	Misc	`conf`	Reconfigurable DSP IP for multimedia applications. ICASSP Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni
2002	—	`conf`	System architecture for error-resilient, embedded JPEG2000 wireless delivery. DSP Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni
2001	—	`conf`	Hierarchical power supply noise evaluation for early power grid design prediction. SLIP Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
2001	—	`conf`	JPEG 2000: finite precision representation and hardware implications. ICECS Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni
2001	—	`conf`	Reconfigurable coprocessor based JPEG 2000 implementation. ICECS Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni
2001	Misc	`conf`	Switching Noise Analysis Framework For High Speed Logic Families. VLSI Design Marco Delaurenti, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
2001	A	`conf`	Synthesis of low-leakage PD-SOI circuits with body-biasing. ISLPED Mario R. Casu, Gianluca Piccinini, Guido Masera, Maurizio Zamboni
2000	A	`conf`	A 50 Mbit/s Iterative Turbo-Decoder. DATE Fabrizio Viglione, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni
2000	C	`conf`	A high accuracy-low complexity model for CMOS delays. ISCAS Mario Roberto Casu, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni
2000	—	`conf`	Noise Safety Design Methodologies. ISQED Mariagrazia Graziano, Marco Delaurenti, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
1999	—	`conf`	A Quantitative Approach to the Design of an Optimized Hardware Interpreter for Java Byte-Code. Applied Informatics Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni
1999	—	`conf`	A global optimization tool for CMOS logic circuits. ICECS Marco Delaurenti, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
1999	—	`conf`	New 2 Gbit/s CMOS I/O pads. Great Lakes Symposium on VLSI Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni
1999	J	`jnl`	VLSI architectures for turbo codes. IEEE Trans. Very Large Scale Integr. Syst. Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni
1998	—	`conf`	A 500 MHz 2d-DWT VLSI processor. EUSIPCO A. Brizio, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni
1998	A	`conf`	Fanout optimization under a submicron transistor-level delay model. ICCAD Pasquale Cocchini, Massoud Pedram, Gianluca Piccinini, Maurizio Zamboni
1997	J	`jnl`	A comprehensive submicrometer MOST delay model and its application to CMOS buffers. IEEE J. Solid State Circuits Pasquale Cocchini, Gianluca Piccinini, Maurizio Zamboni
1996	—	`conf`	A 650 MHz pipelined MAC for DSP applications using a new clocking strategy. EUSIPCO F. Fraternali, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
1993	J	`jnl`	PROXIMA: PROlog eXecutIon MAchine. IEEE J. Solid State Circuits Livio Baldi, Pierluigi Civera, Angela Iurlaro, Guido Masera, Andrea Pagni, Gianluca Piccinini, Rinaldo Poluzzi, Massimo Ruo Roch, Maurizio Zamboni
1992	J	`jnl`	Deflection network: Principles, implementation, services. Eur. Trans. Telecommun. Guido Albertengo, Pierluigi Civera, Renato Lo Cigno, Gianluca Piccinini, Maurizio Zamboni, Flaminio Borgonovo, Luigi Fratta, Giuseppe Panizzardi
1989	J	`jnl`	Implementation studies for a VLSI Prolog coprocessor. IEEE Micro Pierluigi Civera, Gianluca Piccinini, Maurizio Zamboni
1987	A*	`conf`	An Experimental VLSI Prolog Interpreter: Preliminary Measurements and Results. ISCA Pierluigi Civera, Franco Maddaleno, Gianluca Piccinini, Maurizio Zamboni
1987	J	`jnl`	Design considerations on a VLSI Prolog interpreter. Microprocess. Microprogramming Pierluigi Civera, Gianluca Piccinini, Maurizio Zamboni