Giacomo Valente

42 papers A* 1A 1B 4C 7Misc 3Journal 11Unranked 14
YearRankTypeTitle / Venue / Authors
2026 J jnl
Empowering Retail Visitors Through Edge AI: A User-Centered Case Study of Cooperative Totem Systems.
IEEE Access
Gianluca Brilli, Federica Caruso, Giacomo Valente, Alberto Carlevaro, Chiara Garibotto, Jacopo Motta, Vittoriano Muttillo, Damiano Vallocchia, Paolo Burgio
2025 J jnl
A New HW/SW Co-Design Approach for Monitored Systems-on-Chip Development.
ACM Trans. Embed. Comput. Syst.
Giacomo Valente, Vittoriano Muttillo, Luigi Pomante, Daniele Frigioni, Tania Di Mascio
2025 J jnl
Fine-Grained QoS Control via Tightly-Coupled Bandwidth Monitoring and Regulation for FPGA-Based Heterogeneous SoCs.
IEEE Trans. Parallel Distributed Syst.
Giacomo Valente, Gianluca Brilli, Tania Di Mascio, Alessandro Capotondi, Paolo Burgio, Paolo Valente, Andrea Marongiu
2025 J jnl
Leveraging traffic injection and quality-of-service to control the reconfiguration delay.
J. Syst. Archit.
Giacomo Valente, Vittoriano Muttillo, Fabio Federici, Luigi Pomante, Tania Di Mascio
2025 B conf
Multi-Context Execution on a RISC-V Core for Mixed-Criticality Systems.
ETS
Leonardo Fazzini, Giacomo Valente, Fabio Federici, Matthew P. Corbett, Tania Di Mascio
2025 — conf
System-Level Timing Performance Estimation Based on a Unifying HW/SW Performance Metric.
PARMA-DITAM
Vittoriano Muttillo, Vincenzo Stoico, Giacomo Valente, Marco Santic, Luigi Pomante, Daniele Frigioni
2024 J jnl
Analysis of Reconfiguration Delay in Heterogeneous Systems-on-Chip via Traffic Injection.
IEEE Embed. Syst. Lett.
Giacomo Valente, Vittoriano Muttillo, Fabio Federici, Luigi Pomante, Tania Di Mascio
2024 — conf
Invited Paper: On the Granularity of Bandwidth Regulation in FPGA-Based Heterogeneous Systems on Chip.
WCET
Gianluca Brilli, Giacomo Valente, Alessandro Capotondi, Tania Di Mascio, Andrea Marongiu
2024 C conf
SLIDE-x-ML: System-Level Infrastructure for Dataset E-xtraction and Machine Learning Framework for High-Level Synthesis Estimations.
ICCD
Vittoriano Muttillo, Vincenzo Stoico, Marco Santic, Giacomo Valente, Luigi Pomante, Daniele Frigioni
2023 A* conf
Fine-Grained QoS Control via Tightly-Coupled Bandwidth Monitoring and Regulation for FPGA-based Heterogeneous SoCs.
DAC
Gianluca Brilli, Giacomo Valente, Alessandro Capotondi, Paolo Burgio, T. Di Masciov, Paolo Valente, Andrea Marongiu
2023 J jnl
SystemC-based Co-Simulation/Analysis for System-Level Hardware/Software Co-Design.
Comput. Electr. Eng.
Vittoriano Muttillo, Luigi Pomante, Marco Santic, Giacomo Valente
2022 C conf
Sentient Spaces: Intelligent Totem Use Case in the ECSEL FRACTAL Project.
DSD
Federica Caruso, Tania Di Mascio, Daniele Frigioni, Luigi Pomante, Giacomo Valente, Stefano Delucchi, Paolo Burgio, Manuel Di Frangia, Luca Paganin, Chiara Garibotto, Damiano Vallocchia
2021 J jnl
A Composable Monitoring System for Heterogeneous Embedded Platforms.
ACM Trans. Embed. Comput. Syst.
Giacomo Valente, Tiziana Fanni, Carlo Sau, Tania Di Mascio, Luigi Pomante, Francesca Palumbo
2021 C conf
An Investigation of Dynamic Partial Reconfiguration Offloading in Hard Real-Time Systems.
DSD
Gabriella D'Andrea, Giacomo Valente, Luigi Pomante, Tania Di Mascio
2021 J jnl
Design and management of image processing pipelines within CPS: Acquired experience towards the end of the FitOptiVis ECSEL Project.
Microprocess. Microsystems
Carlo Sau, Claudia Rinaldi, Luigi Pomante, Francesca Palumbo, Giacomo Valente, Tiziana Fanni, Marcos Martinez de Alejandro, Frank van der Linden, Twan Basten, Marc Geilen, Geran Peeren, Jirí Kadlec, Pekka Jääskeläinen, Lubomír Bulej, Francisco Barranco, Jukka Saarinen, Tero Säntti, Maria Katiuscia Zedda, Victor Sanchez, Shayan Tabatabaei Nikkhah, Dip Goswami, Guillermo Amat, Lukás Marsík, Mark van Helvoort, Luis Medina, Zaid Al-Ars, Ad de Beer
2021 J jnl
Dynamic Partial Reconfiguration Profitability for Real-Time Systems.
IEEE Embed. Syst. Lett.
Giacomo Valente, Tania Di Mascio, Luigi Pomante, Gabriella D'Andrea
2021 J jnl
Layering the monitoring action for improved flexibility and overhead control: work-in-progress.
CoRR
Giacomo Valente, Tiziana Fanni, Carlo Sau, Francesco Di Battista
2021 Misc conf
MONICA "On-the-Job" Technology-Enhanced Learning Environment: An Empirical Evaluation.
MIS4TEL
Federica Caruso, Tania Di Mascio, Sara Peretti, Luigi Pomante, Giacomo Valente
2021 — conf
MONICA Vision: An Approach, a Model and the Interactive Tools for Cyber-Physical Systems Designers.
CHItaly
Tania Di Mascio, Federica Caruso, Laura Tarantino, Giacomo Valente
2020 Misc conf
An ESL Methodology for HW/SW Co-Design of Monitorable Embedded Systems: the "Design for Monitorability" Project - Work-in-Progress.
CODES+ISSS
Giacomo Valente, Tania Di Mascio, Luigi Pomante, Vincenzo Stoico
2020 C conf
Design and management of image processing pipelines within CPS: 2 years of experience from the FitOptiVis ECSEL Project.
DSD
Luigi Pomante, Francesca Palumbo, Claudia Rinaldi, Giacomo Valente, Carlo Sau, Tiziana Fanni, Frank van der Linden, Twan Basten, Marc Geilen, Geran Peeren, Jirí Kadlec, Pekka Jääskeläinen, Marcos Martinez de Alejandro, Jukka Saarinen, Tero Säntti, Maria Katiuscia Zedda, Victor Sanchez, Dip Goswami, Zaid Al-Ars, Ad de Beer
2020 Misc conf
Layering the monitoring action for improved flexibility and overhead control: work-in-progress.
CODES+ISSS
Giacomo Valente, Tiziana Fanni, Carlo Sau, Francesco Di Battista
2020 C conf
Run-time Monitoring and Trace Analysis Methodology for Component-based Embedded Systems Design Flow.
DSD
Vittoriano Muttillo, Giacomo Valente, Luigi Pomante, Hector Posadas, Javier Merino, Eugenio Villar
2020 A conf
Work-In-Progress: Cyber-Physical Systems and Dynamic Partial Reconfiguration Scalability: opportunities and challenges.
RTSS
Gabriella D'Andrea, Giacomo Valente
2019 — conf
An Intelligent Informative Totem Application Based on Deep CNN in Edge Regime.
ApplePies
Paolo Giammatteo, Giacomo Valente, Alessandro D'Ortenzio
2019 — conf
Self-adaptive loop for CPSs: is the Dynamic Partial Reconfiguration profitable?
MECO
Gabriella D'Andrea, Tania Di Mascio, Giacomo Valente
2018 — conf
CC4CS: an Off-the-Shelf Unifying Statement-Level Performance Metric for HW/SW Technologies.
ICPE Companion
Vittoriano Muttillo, Giacomo Valente, Luigi Pomante, Vincenzo Stoico, Fausto D'Antonio, Fabio Salice
2018 — conf
Criticality-aware Design Space Exploration for Mixed-Criticality Embedded Systems.
ICPE Companion
Vittoriano Muttillo, Giacomo Valente, Luigi Pomante
2018 — conf
Criticality-driven Design Space Exploration for Mixed-Criticality Heterogeneous Parallel Embedded Systems.
PARMA-DITAM@HiPEAC
Vittoriano Muttillo, Giacomo Valente, Luigi Pomante
2018 C conf
Design Space Exploration for Mixed-Criticality Embedded Systems Considering Hypervisor-Based SW Partitions.
DSD
Vittoriano Muttillo, Giacomo Valente, Luigi Pomante
2018 — conf
HEPSIM: An ESL HW/SW co-simulator/analysis tool for heterogeneous parallel embedded systems.
MECO
Daniele Ciambrone, Vittoriano Muttillo, Luigi Pomante, Giacomo Valente
2018 — conf
HEPSYCODE-RT: a Real-Time Extension for an ESL HW/SW Co-Design Methodology.
RAPIDO
Vittoriano Muttillo, Giacomo Valente, Daniele Ciambrone, Vincenzo Stoico, Luigi Pomante
2018 — conf
Injecting hypervisor-based software partitions into Design Space Exploration activities considering mixed-criticality requirements.
MECO
Vittoriano Muttillo, Giacomo Valente
2017 — —
A HW/SW unified approach for embedded systems monitoring.
Giacomo Valente
2017 B conf
An Efficient Performance-Driven Approach for HW/SW Co-Design.
ICPE
Daniele Di Pompeo, Emilio Incerto, Vittoriano Muttillo, Luigi Pomante, Giacomo Valente
2017 — conf
Simulation-Based Analysis of a Hardware Mechanism to Support Isolation in Mixed-Criticality Network on Chip.
EMS
Fabio Federici, Mattia Micozzi, Vittoriano Muttillo, Luigi Pomante, Giacomo Valente
2017 B conf
Time Bands: A Software Approach for Timing Analysis on Resource Constrained Systems.
ICPE
Giacomo Valente, Marco Rotondi, Vittoriano Muttillo
2016 C conf
A Flexible Profiling Sub-System for Reconfigurable Logic Architectures.
PDP
Giacomo Valente, Vittoriano Muttillo, Luigi Pomante, Fabio Federici, Marco Faccio, Andrea Moro, Serenella Ferri, Carlo Tieri
2016 J jnl
A design methodology for soft-core platforms on FPGA with SMP Linux, OpenMP support, and distributed hardware profiling system.
EURASIP J. Embed. Syst.
Vittoriano Muttillo, Giacomo Valente, Fabio Federici, Luigi Pomante, Marco Faccio, Carlo Tieri, Serenella Ferri
2016 — conf
Design and validation of multi-core embedded systems under time-to-prototype and high performance constraints.
RTSI
Marco Faccio, Fabio Federici, Giuseppe Marini, Vittoriano Muttillo, Luigi Pomante, Giacomo Valente
2015 B conf
A framework for integrated monitoring of real-time embedded SoC.
FPL
Giacomo Valente
2015 — conf
Hardware performance sniffers for embedded systems profiling.
WISES
Andrea Moro, Fabio Federici, Giacomo Valente, Luigi Pomante, Marco Faccio, Vittoriano Muttillo