Gi-Ho Park

35 papers A 1B 1C 4Misc 3Journal 21Unranked 4
YearRankTypeTitle / Venue / Authors
2024 — conf
SK Hynix AI-Specific Computing Memory Solution: From AiM Device to Heterogeneous AiMX-xPU System for Comprehensive LLM Inference.
HCS
Guhyun Kim, Jinkwon Kim, Nahsung Kim, Woojae Shin, Jongsoon Won, Hyunha Joo, Haerang Choi, Byeongju An, Gyeongcheol Shin, Dayeon Yun, Jeongbin Kim, Changhyun Kim, Ilkon Kim, Jaehan Park, Yosub Song, Byeongsu Yang, Hyeongdeok Lee, Seungyeong Park, Wonjun Lee, Seonghun Kim, Yonghoon Park, Yousub Jung, Gi-Ho Park, Euicheol Lim
2017 J jnl
NVM Way Allocation Scheme to Reduce NVM Writes for Hybrid Cache Architecture in Chip-Multiprocessors.
IEEE Trans. Parallel Distributed Syst.
Ju Hee Choi, Gi-Ho Park
2016 J jnl
Demand-Aware NVM Capacity Management Policy for Hybrid Cache Architecture.
Comput. J.
Ju Hee Choi, Gi-Ho Park
2015 J jnl
Data Classification Management with its Interfacing Structure for Hybrid SLC/MLC PRAM Main Memory.
Comput. J.
Sung-In Jang, Su-Kyung Yoon, Kihyun Park, Gi-Ho Park, Shin-Dug Kim
2014 J jnl
Adaptive replacement policy for hybrid cache architecture.
IEICE Electron. Express
Ju Hee Choi, Gi-Ho Park
2012 — conf
Performance and energy-efficiency analysis of hybrid cache memory based on SRAM-MRAM.
ISOCC
Byung-Min Lee, Gi-Ho Park
2010 J jnl
An instruction-systolic programmable shader architecture for multi-threaded 3D graphics processing.
J. Parallel Distributed Comput.
Jung-Wook Park, Hoon-Mo Yang, Gi-Ho Park, Shin-Dug Kim, Charles C. Weems
2010 J jnl
Design and implementation of Performance Analysis Unit (PAU) for AXI-based multi-core System on Chip (SOC).
Microprocess. Microsystems
Hyun-min Kyung, Gi-Ho Park, Jong Wook Kwak, Tae-Jin Kim, Sung-Bae Park
2010 J jnl
Fully digital clock frequency doubler.
IEICE Electron. Express
Gunok Jung, Gi-Ho Park, Ukrae Cho, Jae-Cheol Son
2009 J jnl
A Way Enabling Mechanism Based on the Branch Prediction Information for Low Power Instruction Cache.
IEICE Trans. Electron.
Gi-Ho Park, Jung-Wook Park, Hoi-Jin Lee, Gunok Jung, Sung-Bae Park, Shin-Dug Kim
2009 J jnl
An integrated mapping table for hybrid FTL with fault-tolerant address cache.
IEICE Electron. Express
Jung-Wook Park, Seung-Ho Park, Gi-Ho Park, Shin-Dug Kim
2009 J jnl
Low-Power Embedded Processor Design Using Branch Direction.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Gi-Ho Park, Jung-Wook Park, Gunok Jung, Shin-Dug Kim
2009 J jnl
Sub-grouped superblock management for high-performance flash storages.
IEICE Electron. Express
Jung-Wook Park, Gi-Ho Park, Charles C. Weems, Shin-Dug Kim
2008 J jnl
Power and Skew Aware Point Diffusion Clock Network.
IEICE Trans. Electron.
Gunok Jung, Chunghee Kim, Kyoungkuk Chae, Gi-Ho Park, Sung-Bae Park
2007 — conf
An efficient scheme for parallelizing fast search algorithm on SIMD architecture in H.264/AVC.
PDCS
Jung-Min Park, Jung-Wook Park, Cheong-Ghil Kim, Gi-Ho Park, Shin-Dug Kim
2007 J jnl
Cooperative Cache System: A Low Power Cache System for Embedded Processors.
IEICE Trans. Electron.
Gi-Ho Park, Kil-Whan Lee, Tack-Don Han, Shin-Dug Kim
2007 Misc conf
Performance monitor unit design for an AXI-based multi-core SoC platform.
SAC
Hyun-min Kyung, Gi-Ho Park, Jong Wook Kwak, Wookyeong Jeong, Tae-Jin Kim, Sung-Bae Park
2006 J jnl
A deterministic way-prediction scheme using power-aware replacement policy.
Microprocess. Microsystems
Jung-Wook Park, Gi-Ho Park, Sung-Bae Park, Shin-Dug Kim
2006 — conf
Low-Power Data Cache Architecture by Address Range Reconfiguration for Multimedia Applications.
Asia-Pacific Computer Systems Architecture Conference
Hoon-Mo Yang, Gi-Ho Park, Shin-Dug Kim
2006 C conf
Practice and Experience of an Embedded Processor Core Modeling.
HPCC
Gi-Ho Park, Sung Woo Chung, Han-Jong Kim, Jung-Bin Im, Jung-Wook Park, Shin-Dug Kim, Sung-Bae Park
2006 J jnl
Sim-ARM1136: A case study on the accuracy of the cycle-accurate simulator.
Microprocess. Microsystems
Sung Woo Chung, Gi-Ho Park, Hyo-Joong Suh, Han-Jong Kim, Jung-Bin Im, Jung-Wook Park, Sung-Bae Park
2005 J jnl
A new NAND-type flash memory package with smart buffer system for spatial and temporal localities.
J. Syst. Archit.
Jung-Hoon Lee, Gi-Ho Park, Shin-Dug Kim
2005 — —
p-Refinement Techniques for Vector Finite Elements in Electromagnetics.
Gi-Ho Park
2004 J jnl
A Low-Power Branch Predictor for Embedded Processors.
IEICE Trans. Inf. Syst.
Sung Woo Chung, Gi-Ho Park, Sung-Bae Park
2004 J jnl
A Low-Power Tournament Branch Predictor.
IEICE Trans. Inf. Syst.
Sung Woo Chung, Gi-Ho Park, Sung-Bae Park
2004 J jnl
Dynamic and selective low power data TLB system.
Microprocess. Microsystems
Jung-Hoon Lee, Gi-Ho Park, Shin-Dug Kim
2004 C conf
Power-Aware Deterministic Block Allocation for Low-Power Way-Selective Cache Structure.
ICCD
Jung-Wook Park, Gi-Ho Park, Sung-Bae Park, Shin-Dug Kim
2003 A conf
A selective filter-bank TLB system.
ISLPED
Jung-Hoon Lee, Gi-Ho Park, Sung-Bae Park, Shin-Dug Kim
2003 C conf
An Adaptive Multi-Module Cache with Hardware Prefetching Mechanism for Multimedia Applications.
PDP
Jung-Hoon Lee, Gi-Ho Park, Shin-Dug Kim
2003 Misc conf
Appliaction-Specific Data Cache Systems.
CATA
Jung-Hoon Lee, Gi-Ho Park, Shin-Dug Kim
2002 C conf
An Advanced Filtering TLB for Low Power Consumption.
SBAC-PAD
Jin-Hyuck Choi, Jung-Hoon Lee, Gi-Ho Park, Shin-Dug Kim
2000 Misc conf
A Dual Data Cache System to Reflect the Principle of Locality Effectively.
PDPTA
Gi-Ho Park, Kil-Whan Lee, Tack-Don Han, Shin-Dug Kim
2000 B conf
A Power Efficient Cache Structure for Embedded Processors Based on the Dual Cache Structure.
LCTES
Gi-Ho Park, Kil-Whan Lee, Jae-Hyuk Lee, Tack-Don Han, Shin-Dug Kim
1998 J jnl
Methods to improve performance of instruction prefetching through balanced improvement of two primary performance factors.
J. Syst. Archit.
Gi-Ho Park, Oh-Young Kwon, Tack-Don Han, Shin-Dug Kim, Sung-Bong Yang
1996 J jnl
A compiler optimization to reduce execution time of loop nest.
SIGARCH Comput. Archit. News
Oh-Young Kwon, Gi-Ho Park, Tack-Don Han