Ghavam G. Shahidi

16 papers A 1Journal 9Unranked 5
YearRankTypeTitle / Venue / Authors
2020 J jnl
Chip Power-Frequency Scaling in 10/7nm Node.
IEEE Access
Phil Oldiges, Reinaldo A. Vega, Henry K. Utomo, Nick A. Lanzillo, Thomas Wassick, Juntao Li, Junli Wang, Ghavam G. Shahidi
2020 J jnl
EM-Side-Channel Resistant Symmetric-Key Authentication Mechanism for Small Devices.
IACR Cryptol. ePrint Arch.
Rick Boivie, Charanjit S. Jutla, Daniel J. Friedman, Ghavam G. Shahidi
2019 J jnl
Chip Power Scaling in Recent CMOS Technology Nodes.
IEEE Access
Ghavam G. Shahidi
2019 — conf
Slow-Down in Power Scaling and the End of Moore's Law?
VLSI-DAT
Ghavam G. Shahidi
2013 — conf
From 2D-planar to 3D-non-planar device architecture: A scalable path forward?
CICC
Ghavam G. Shahidi
2010 — conf
Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond.
ISSCC
Ali Khaki-Firooz, Kangguo Cheng, Basanth Jagannathan, Pranita Kulkarni, Jeffrey W. Sleight, Davood Shahrjerdi, Josephine B. Chang, Sungjae Lee, Junjun Li, Huiming Bu, Robert Gauthier, Bruce Doris, Ghavam G. Shahidi
2007 — conf
Evolution of CMOS Technology at 32 nm and Beyond.
CICC
Ghavam G. Shahidi
2006 J jnl
Optimizing CMOS technology for maximum performance.
IBM J. Res. Dev.
David J. Frank, Wilfried Haensch, Ghavam G. Shahidi, Omer H. Dokumaci
2002 J jnl
SOI technology for the GHz era.
IBM J. Res. Dev.
Ghavam G. Shahidi
1999 — conf
Device and circuit design issues in SOI technology.
CICC
Ghavam G. Shahidi, Atul Ajmera, Fariborz Assaderaghi, Ronald J. Bolam, Harold Hovel, Effendi Leobandung, Werner Rausch, Devendra Sadana, Dominic Schepis, Lawrence F. Wagner, Larry Wissel, Kun Wu, Bijan Davai
1997 J jnl
SRAM bitline circuits on PD SOI: advantages and concerns.
IEEE J. Solid State Circuits
Jente B. Kuang, Somnuk Ratanaphanyarat, Mary Jo Saccamango, Louis L.-C. Hsu, Roy C. Flaker, Lawrence F. Wagner, Shao-Fu Sanford Chu, Ghavam G. Shahidi
1996 A conf
250-600 Mhz 12b digital filters in 0.8-0.25um Bulk and SOI CMOS technologies.
ISLPED
Lars E. Thon, Ghavam G. Shahidi, Werner Rausch, Gerald P. Coleman, Denny D. Tang, Dominic Schepis, Ronald Schulz, Fariborz Assadaraghi
1995 J jnl
A half-micron CMOS logic generation.
IBM J. Res. Dev.
Charles W. Koburger III, William F. Clark, James W. Adkisson, Eric Adler, Paul E. Bakeman, Albert S. Bergendahl, Alan B. Botula, W. Chang, Bijan Davari, John H. Givens, Howard H. Hansen, Steven J. Holmes, David V. Horak, Chung Hon Lam, Jerome B. Lasky, Stephen E. Luce, Randy W. Mann, Glen L. Miles, James S. Nakos, Edward J. Nowak, Ghavam G. Shahidi, Yuan Taur, Francis R. White, Matthew R. Wordeman
1995 J jnl
CMOS scaling for high performance and low power-the next ten years.
Proc. IEEE
Bijan Davari, Robert H. Dennard, Ghavam G. Shahidi
1995 J jnl
CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications.
IBM J. Res. Dev.
Ghavam G. Shahidi, James D. Warnock, James Comfort, Stephen E. Fischer, Patricia A. McFarland, Alexandre Acovic, Terry I. Chappell, Barbara A. Chappell, Tak H. Ning, Carl J. Anderson, Robert H. Dennard, Jack Y.-C. Sun, Michael R. Polcari, Bijan Davari
1989 — —
Non-stationary transport effects in deep sub-micron channel Si mosfets.
Ghavam G. Shahidi