Ghassem Jaberipur

64 papers C 9Misc 1Journal 52Unranked 2
YearRankTypeTitle / Venue / Authors
2025 J jnl
Auto Digit Selection for Most Significant Digit First Multiplication.
IEEE Embed. Syst. Lett.
Saeid Gorgin, Ghassem Jaberipur, Jeong-A Lee, Seokjoo Shin, Jungrae Kim
2025 J jnl
Balanced Modular Addition for the Moduli Set $ \{2^{q},2^{q}\mp 1,2^{2q}+1\}${2q,2q∓1,22q+1} via Moduli-($ 2^{q}\mp \sqrt{-1}$2q∓-1) Adders.
IEEE Trans. Computers
Ghassem Jaberipur, Elham Rahman, Jeong-A Lee
2025 J jnl
Design of energy-efficient and high-speed hybrid decimal adder.
J. Supercomput.
Negin Mashayekhi, Ghassem Jaberipur, Mohammad Reza Reshadinezhad, Shekoofeh Moghimi
2025 C conf
Poster: Integration of Wearable and Affective Computing via Abstraction and Decision Fusion Architecture.
WoWMoM
Mohammadreza Najafi, Mohammad K. Fallah, Saeid Gorgin, Ghassem Jaberipur, Jeong-A Lee
2024 J jnl
Forward and Reverse Converters for the Moduli-Set {2
CoRR
Ghassem Jaberipur, Bardia Nadimi, R. Kazemi, Jeong-A Lee
2024 J jnl
Low-cost constant time signed digit selection for most significant bit first multiplication.
Microprocess. Microsystems
Ghassem Jaberipur, Saeid Gorgin, Jeong-A Lee
2024 J jnl
Modulo-(2
CoRR
Ghassem Jaberipur, Bardia Nadimi, Jeong-A Lee
2024 C conf
Montgomery Modular Multiplication via Single-Base Residue Number Systems.
ARITH
Zabihollah Ahmadpour, Ghassem Jaberipur, Jeong-A Lee
2024 J jnl
RNPE: An MSDF and Redundant Number System-Based DNN Accelerator Engine.
IEEE Access
Iraj Moghaddasi, Ghassem Jaberipur, Danial Javaheri, Byeong-Gyu Nam
2024 J jnl
Sparse Matrix-Vector Multiplication Based on Online Arithmetic.
IEEE Access
Sahar Moradi Cherati, Ghassem Jaberipur, Leonel Sousa
2023 J jnl
A Parallel Prefix Modulo-(2
IEEE Trans. Circuits Syst. II Express Briefs
Ghassem Jaberipur, Dariush Badri, Jeong-A Lee
2023 C conf
Modulo-(2
ARITH
Ghassem Jaberipur, Saeid Gorgin, Navid Ahamadian, Jeong-A Lee
2022 J jnl
Efficient variable-coefficient RNS-FIR filters with no restriction on the moduli set.
Signal Image Video Process.
Armin Belghadr, Ghassem Jaberipur
2022 J jnl
Impact of Radix-10 Redundant Digit Set [-6, 9] on Basic Decimal Arithmetic Operations.
IEEE Trans. Very Large Scale Integr. Syst.
Ghassem Jaberipur, Farzad Ghazanfari
2022 J jnl
Up to $8k$8k-bit Modular Montgomery Multiplication in Residue Number Systems With Fast 16-bit Residue Channels.
IEEE Trans. Computers
Zabihollah Ahmadpour, Ghassem Jaberipur
2020 J jnl
Balanced $(3+2\log n)\Delta G$ Adders for Moduli Set $\{{2}^{n+1}, 2^{n}+2^{n-1}-1, 2^{n+1}-1\}$.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl.
Ghassem Jaberipur, Bardia Nadimi
2020 J jnl
Complex exponential functions: A high-precision hardware realization.
Integr.
Adel Hosseiny, Ghassem Jaberipur
2020 J jnl
Design of an efficient fully nonvolatile and radiation-hardened majority-based magnetic full adder using FinFET/MTJ.
Microelectron. J.
Sina Bakhtavari Mamaghani, Mohammad Hossein Moaiyeri, Ghassem Jaberipur
2020 J jnl
Fast division in the residue number system {2
Comput. Electr. Eng.
Zeinab Torabi, Ghassem Jaberipur, Armin Belghadr
2020 J jnl
Majority-Logic, its applications, and atomic-scale embodiments.
Comput. Electr. Eng.
Behrooz Parhami, Dariush Abedi, Ghassem Jaberipur
2019 J jnl
Impact of diminished-1 encoding on residue number systems arithmetic units and converters.
Comput. Electr. Eng.
Ghassem Jaberipur, Armin Belghadr, Saeed Nejati
2019 C conf
Modulo-(2^n+3) Parallel Prefix Addition via Diminished-3 Representation of Residues.
ARITH
Ghassem Jaberipur, Sahar Moradi Cherati
2018 J jnl
Adapting Computer Arithmetic Structures to Sustainable Supercomputing in Low-Power, Majority-Logic Nanotechnologies.
IEEE Trans. Sustain. Comput.
Ghassem Jaberipur, Behrooz Parhami, Dariush Abedi
2018 J jnl
Decimal Full Adders Specially Designed for Quantum-Dot Cellular Automata.
IEEE Trans. Circuits Syst. II Express Briefs
Dariush Abedi, Ghassem Jaberipur
2018 J jnl
Extended Redundant-Digit Instruction Set for Energy-Efficient Processors.
ACM Trans. Embed. Comput. Syst.
Saba Amanollahi, Ghassem Jaberipur
2018 J jnl
FIR Filter Realization via Deferred End-Around Carry Modular Addition.
IEEE Trans. Circuits Syst. I Regul. Pap.
Armin Belghadr, Ghassem Jaberipur
2017 J jnl
(5 + 2⌈log n⌉)ΔG diminished-1 modulo-(2
Comput. Electr. Eng.
Ghassem Jaberipur, Armin Belghadr
2017 J jnl
Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Saba Amanollahi, Ghassem Jaberipur
2017 J jnl
Fast Energy Efficient Radix-16 Sequential Multiplier.
IEEE Embed. Syst. Lett.
Saba Amanollahi, Ghassem Jaberipur
2017 J jnl
Radix-8 full adder in QCA with single clock-zone carry propagation delay.
Microprocess. Microsystems
Milad Sangsefidi, Dariush Abedi, Ghassem Jaberipur
2017 J jnl
Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication.
IEEE Trans. Very Large Scale Integr. Syst.
Saeid Gorgin, Ghassem Jaberipur
2016 C conf
A Formulation of Fast Carry Chains Suitable for Efficient Implementation with Majority Elements.
ARITH
Ghassem Jaberipur, Behrooz Parhami, Dariush Abedi
2016 J jnl
Conditional speculative mixed decimal/binary adders via binary-coded-chiliad encoding.
Comput. Electr. Eng.
Morteza Dorrigiv, Ghassem Jaberipur
2016 J jnl
Decimal Goldschmidt: A hardware algorithm for radix-10 division.
Comput. Electr. Eng.
Adel Hosseiny, Ghassem Jaberipur
2016 J jnl
Decimal Square Root: Algorithm and Hardware Implementation.
Circuits Syst. Signal Process.
Adel Hosseiny, Ghassem Jaberipur
2016 J jnl
Fast low energy RNS comparators for 4-moduli sets {2
Integr.
Zeinab Torabi, Ghassem Jaberipur
2016 J jnl
Low-Power/Cost RNS Comparison via Partitioning the Dynamic Range.
IEEE Trans. Very Large Scale Integr. Syst.
Zeinab Torabi, Ghassem Jaberipur
2015 J jnl
(4+2 log n)ΔG Parallel Prefix Modulo-(2
IEEE Trans. Circuits Syst. II Express Briefs
Ghassem Jaberipur, Seyed Hamed Fatemi Langroudi
2015 J jnl
A New Residue Number System with 5-Moduli Set: {2
Comput. J.
HamidReza Ahmadifar, Ghassem Jaberipur
2015 J jnl
Comment on "High Speed Parallel Decimal Multiplication With Redundant Internal Encodings".
IEEE Trans. Computers
Saeid Gorgin, Ghassem Jaberipur
2015 C conf
Modulo-(2
ARITH
Seyed Hamed Fatemi Langroudi, Ghassem Jaberipur
2014 J jnl
A ROM-less reverse RNS converter for moduli set {2
IET Comput. Digit. Tech.
Ghassem Jaberipur, HamidReza Ahmadifar
2014 — conf
Double {0, 1, 2} representation modulo-(2
IWSSIP
Seyed Hamed Fatemi Langroudi, Ghassem Jaberipur
2014 J jnl
Efficient ASIC and FPGA Implementation of Binary-Coded Decimal Digit Multipliers.
Circuits Syst. Signal Process.
Saeid Gorgin, Ghassem Jaberipur, Reza Hashemi Asl
2014 J jnl
Low area/power decimal addition with carry-select correction and carry-select sum-digits.
Integr.
Morteza Dorrigiv, Ghassem Jaberipur
2012 J jnl
Efficient realisation of arithmetic algorithms with weighted collection of posibits and negabits.
IET Comput. Digit. Tech.
Ghassem Jaberipur, Behrooz Parhami
2012 J jnl
Improved CMOS (4; 2) compressor designs for parallel multipliers.
Comput. Electr. Eng.
Abdoreza Pishvaie, Ghassem Jaberipur, Ali Jahanian
2011 C conf
A Family of High Radix Signed Digit Adders.
IEEE Symposium on Computer Arithmetic
Saeid Gorgin, Ghassem Jaberipur
2011 J jnl
Decimal CORDIC Rotation based on Selection by Rounding: Algorithm and Architecture.
Comput. J.
Amir Kaivani, Ghassem Jaberipur
2011 J jnl
Improving the speed of decimal division.
IET Comput. Digit. Tech.
Amir Kaivani, Adel Hosseiny, Ghassem Jaberipur
2011 — conf
On building general modular adders from standard binary arithmetic components.
ACSCC
Ghassem Jaberipur, Behrooz Parhami, Saeed Nejati
2010 J jnl
An improved maximally redundant signed digit adder.
Comput. Electr. Eng.
Ghassem Jaberipur, Saeid Gorgin
2010 J jnl
Fully redundant decimal addition and subtraction using stored-unibit encoding.
Integr.
Amir Kaivani, Ghassem Jaberipur
2010 J jnl
Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value.
IEEE Trans. Computers
Ghassem Jaberipur, Behrooz Parhami, Saeid Gorgin
2009 J jnl
A fully redundant decimal adder and its application in parallel decimal multipliers.
Microelectron. J.
Saeid Gorgin, Ghassem Jaberipur
2009 C conf
Fully Redundant Decimal Arithmetic.
IEEE Symposium on Computer Arithmetic
Saeid Gorgin, Ghassem Jaberipur
2009 J jnl
Improving the Speed of Parallel Decimal Multiplication.
IEEE Trans. Computers
Ghassem Jaberipur, Amir Kaivani
2009 C conf
Unified Approach to the Design of Modulo-(2
IEEE Symposium on Computer Arithmetic
Ghassem Jaberipur, Behrooz Parhami
2008 Misc conf
A Nonspeculative Maximally Redundant Signed Digit Adder.
CSICC
Ghassem Jaberipur, Saeid Gorgin
2008 J jnl
Constant-time addition with hybrid-redundant numbers: Theory and implementations.
Integr.
Ghassem Jaberipur, Behrooz Parhami
2007 J jnl
Binary-coded decimal digit multipliers.
IET Comput. Digit. Tech.
Ghassem Jaberipur, Amir Kaivani
2007 J jnl
Stored-transfer representations with weighted digit-set encodings for ultrahigh-speed arithmetic.
IET Circuits Devices Syst.
Ghassem Jaberipur, Behrooz Parhami
2006 J jnl
An Efficient Universal Addition Scheme for All Hybrid-Redundant Representations with Weighted Bit-Set Encoding.
J. VLSI Signal Process.
Ghassem Jaberipur, Behrooz Parhami, Mohammad Ghodsi
2005 J jnl
Weighted two-valued digit-set encodings: unifying efficient hardware representation schemes for redundant number systems.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ghassem Jaberipur, Behrooz Parhami, Mohammad Ghodsi