Gerhard W. Dueck

100 papers A* 1A 5B 3C 14Misc 1Journal 32Unranked 44

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	Using AI to help Preserve Indigenous Oral Histories. IHTC Gerhard W. Dueck
2023	—	`conf`	Java Runtime Optimization for Copying Arrays on AArch64. MECO Siri Sahithi Ponangi, Gerhard W. Dueck, Kenneth B. Kent, Daryl Maier, Kazuhiro Konno
2022	—	`conf`	Evaluating the Performance of the Eclipse OpenJ9 JVM JIT Compiler on AArch64. CCECE Aaron Graham, Jean-Philippe Legault, Hillary Soontiens, Julie Brown, Stephen A. MacKay, Gerhard W. Dueck, Kenneth B. Kent, Kazuhiro Konno, Daryl Maier
2022	J	`jnl`	Template-based mapping of reversible circuits to IBM quantum computers. Microprocess. Microsystems Philipp Niemann, Alexandre A. A. de Almeida, Gerhard W. Dueck, Rolf Drechsler
2021	—	`conf`	A lightweight code storage container for the eclipse OMR ahead-of-time compiler. CASCON Damian Diago D'monte, Georgiy Krylov, Younes Manton, Gerhard W. Dueck, Kenneth B. Kent
2021	J	`jnl`	Adaptive Integer Linear Programming Model for Optimal Qubit Permutation. IEEE Des. Test Alexandre A. A. de Almeida, Gerhard W. Dueck
2021	—	`conf`	Ahead-of-time compilation in eclipse OMR on example of WebAssembly. CASCON Georgiy Krylov, Petar Jelenkovic, Mark Thom, Gerhard W. Dueck, Kenneth B. Kent, Younes Manton, Daryl Maier
2021	—	`conf`	Descending Order Transformation-based Synthesis of MVL Reversible Circuits. ISMVL D. Michael Miller, Gerhard W. Dueck
2021	J	`jnl`	Exploring the Potential Benefits of Alternative Quantum Computing Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Arighna Deb, Gerhard W. Dueck, Robert Wille
2021	J	`jnl`	Function translations and search-based transformation for MVL reversible circuit synthesis. Sci. Comput. Program. D. Michael Miller, Gerhard W. Dueck
2020	—	`conf`	An ELF-based storage option for the eclipse OMR ahead-of-time compiler. CASCON Damian Diago D'monte, Georgiy Krylov, Daryl Maier, Gerhard W. Dueck, Kenneth B. Kent
2020	—	`conf`	Cold Object Identification and Segregation using Page Protection and Profiling. MECO Abhijit Taware, Kenneth B. Kent, Gerhard W. Dueck, Charlie Gracie
2020	C	`conf`	Design Space Exploration in the Mapping of Reversible Circuits to IBM Quantum Computers. DSD Philipp Niemann, Alexandre A. A. de Almeida, Gerhard W. Dueck, Rolf Drechsler
2020	C	`conf`	Search-Based Transformation Synthesis for 3-Valued Reversible Circuits. RC D. Michael Miller, Gerhard W. Dueck
2020	—	`conf`	The Evolution of Garbage Collection in V8: Google's JavaScript Engine. MECO Georgiy Krylov, Maria Patrou, Gerhard W. Dueck, Joran Siu
2020	A	`conf`	Towards Exploring the Potential of Alternative Quantum Computing Architectures. DATE Arighna Deb, Gerhard W. Dueck, Robert Wille
2019	—	`conf`	Ahead-of-time compilation in OMR: overview and first steps. CASCON Georgiy Krylov, Gerhard W. Dueck, Kenneth B. Kent, Daryl Maier, Irwin D'Souza
2019	—	`conf`	CNOT Gate Mappings to Clifford+T Circuits in IBM Architectures. ISMVL Alexandre Araujo Amaral de Almeida, Gerhard W. Dueck, Alexandre C. R. da Silva
2019	J	`jnl`	CNOT Gate Optimizations via Qubit Permutations for IBM's Quantum Architectures. J. Low Power Electron. Alexandre A. A. de Almeida, Gerhard W. Dueck, Alexandre C. R. da Silva
2019	C	`conf`	Efficient Realization of Toffoli and NCV Circuits for IBM QX Architectures. RC Alexandre A. A. de Almeida, Gerhard W. Dueck, Alexandre César Rodrigues da Silva
2019	—	`conf`	Finding optimal qubit permutations for IBM's quantum computer architectures. SBCCI Alexandre A. A. de Almeida, Gerhard W. Dueck, Alexandre C. R. da Silva
2018	—	`conf`	A survey of ahead-of-time technologies in dynamic language environments. CASCON Mark Thom, Gerhard W. Dueck, Kenneth B. Kent, Daryl Maier
2018	—	`conf`	DISTIL: a distributed in-memory data processing system for location-based services. SIGSPATIAL/GIS Maria Patrou, Md. Mahbub Alam, Puya Memarzia, Suprio Ray, Virendra C. Bhavsar, Kenneth B. Kent, Gerhard W. Dueck
2018	—	`conf`	Efficient Realizations of CNOT gates in IBM's Quantum Computers. ISED Alexandre A. A. de Almeida, Gerhard W. Dueck, Alexandre C. R. da Silva
2018	B	`conf`	NUMA Awareness: Improving Thread and Memory Management. SEAA Maria Patrou, Kenneth B. Kent, Gerhard W. Dueck, Charlie Gracie, Aleksandar Micic
2018	C	`conf`	Optimization of Circuits for IBM's Five-Qubit Quantum Computers. DSD Gerhard W. Dueck, Anirban Pathak, Md. Mazder Rahman, Abhishek Shukla, Anindita Banerjee
2018	J	`jnl`	Optimization of Circuits for IBM's five-qubit Quantum Computers. CoRR Gerhard W. Dueck, Anirban Pathak, Md. Mazder Rahman, Abhishek Shukla, Anindita Banerjee
2018	—	`conf`	Persistent memory storage of cold regions in the OpenJ9 Java virtual machine. CASCON Scott Ryan Young, Michael Flawn, Gerhard W. Dueck, Kenneth B. Kent, Charlie Gracie
2018	—	`conf`	Reversible Circuit Optimization Based on Tabu Search. ISMVL Alexandre A. A. de Almeida, Gerhard W. Dueck, Alexandre C. R. da Silva
2018	J	`jnl`	Synthesis of Majority Expressions through Primitive Function Manipulation. CoRR Evandro C. Ferraz, Jeferson de Lima Muniz, Alexandre C. R. da Silva, Gerhard W. Dueck
2017	J	`jnl`	Building a Completely Reversible Computer. CoRR Martin Lukac, Gerhard W. Dueck, Michitaka Kameyama, Anirban Pathak
2017	J	`jnl`	Cold object identification in the Java virtual machine. Softw. Pract. Exp. Kim T. Briggs, Baoguo Zhou, Gerhard W. Dueck
2016	C	`conf`	A Fast Symbolic Transformation Based Algorithm for Reversible Logic Synthesis. RC Mathias Soeken, Gerhard W. Dueck, D. Michael Miller
2016	C	`conf`	An extension of transformation-based reversible and quantum circuit synthesis. ISCAS Mathias Soeken, Gerhard W. Dueck, Md. Mazder Rahman, D. Michael Miller
2016	J	`jnl`	Ancilla-free synthesis of large reversible functions using binary decision diagrams. J. Symb. Comput. Mathias Soeken, Laura Tague, Gerhard W. Dueck, Rolf Drechsler
2016	—	`conf`	Fault Detection in Parity Preserving Reversible Circuits. ISMVL Nils Przigoda, Gerhard W. Dueck, Robert Wille, Rolf Drechsler
2016	J	`jnl`	GarCoSim: A Framework for Automated Memory Management Research and Evaluation. EAI Endorsed Trans. Scalable Inf. Syst. Konstantin Nasartschuk, Marcel Dombrowski, Tristan Basa, Md. Mazder Rahman, Kenneth B. Kent, Gerhard W. Dueck
2016	—	`conf`	Integrated Synthesis of Linear Nearest Neighbor Ancilla-Free MCT Circuits. ISMVL Md. Mazder Rahman, Gerhard W. Dueck, Anupam Chattopadhyay, Robert Wille
2016	—	`conf`	Thread-group based local heap garbage collection in a simulated runtime environment. CCECE Marcel Dombrowski, Konstantin Nasartschuk, Kenneth B. Kent, Gerhard W. Dueck, Charlie Gracie
2016	—	`conf`	Trace Files for Automatic Memory Management Systems. VST@SANER Md. Mazder Rahman, Konstantin Nasartschuk, Kenneth B. Kent, Gerhard W. Dueck
2015	—	`conf`	A survey on object cache locality in automated memory management systems. CCECE Marcel Dombrowski, Konstantin Nasartschuk, Kenneth B. Kent, Gerhard W. Dueck
2015	J	`jnl`	Cold Object Identification in the Java Virtual Machine. CoRR Kim T. Briggs, Baoguo Zhou, Gerhard W. Dueck
2015	—	`conf`	Dynamic Template Matching with Mixed-Polarity Toffoli Gates. ISMVL Md. Mazder Rahman, Mathias Soeken, Gerhard W. Dueck
2015	—	`conf`	Metis: a smart memory allocator using historical reclamation information. ICOOOLPS@ECOOP Shijie Xu, Qi Guo, Gerhard W. Dueck, David Bremner, Yang Wang
2015	C	`conf`	Reversible circuit rewriting with simulated annealing. VLSI-SoC Nabila Abdessaied, Mathias Soeken, Gerhard W. Dueck, Rolf Drechsler
2015	J	`jnl`	Self-Inverse Functions and Palindromic Circuits. CoRR Mathias Soeken, Michael Kirkedal Thomsen, Gerhard W. Dueck, D. Michael Miller
2015	J	`jnl`	Synthesis of Linear Nearest Neighbor Quantum Circuits. CoRR Md. Mazder Rahman, Gerhard W. Dueck
2014	J	`jnl`	An Algorithm for Quantum Template Matching. ACM J. Emerg. Technol. Comput. Syst. Md. Mazder Rahman, Gerhard W. Dueck, Joseph D. Horton
2014	J	`jnl`	Ancilla-free synthesis of large reversible functions using binary decision diagrams. CoRR Mathias Soeken, Laura Tague, Gerhard W. Dueck, Rolf Drechsler
2014	J	`jnl`	Challenges and advances in Toffoli network optimisation. IET Comput. Digit. Tech. Gerhard W. Dueck
2014	C	`conf`	Minimal Designs of Reversible Sequential Elements. RC Anindita Banerjee, Anirban Pathak, Gerhard W. Dueck
2013	C	`ed.`	Reversible Computation - 5th International Conference, RC 2013, Victoria, BC, Canada, July 4-5, 2013. Proceedings RC Gerhard W. Dueck, D. Michael Miller
2012	B	`conf`	An algorithm to find quantum templates. IEEE Congress on Evolutionary Computation Md. Mazder Rahman, Gerhard W. Dueck
2012	J	`jnl`	Design and Optimization of Single and Multiple-Loop Reversible and Quantum Feedback Circuits. J. Circuits Syst. Comput. Majid Mohammadi, Aliakbar Niknafs, Mohammad Eshghi, Gerhard W. Dueck
2012	—	`conf`	Optimal Quantum Circuits of Three Qubits. ISMVL Md. Mazder Rahman, Gerhard W. Dueck
2012	C	`conf`	Properties of Quantum Templates. RC Md. Mazder Rahman, Gerhard W. Dueck
2012	—	`conf`	Synthesis of Toffoli Networks: Status and Challenges. ISED Gerhard W. Dueck
2012	J	`jnl`	Toffoli Gate Implementation Using The Billiard Ball Model. J. Multiple Valued Log. Soft Comput. Hadi Hosseini, Gerhard W. Dueck
2011	J	`jnl`	Debugging reversible circuits. Integr. Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
2011	C	`conf`	Optimization of Reversible Circuits Using Reconfigured Templates. RC Md. Mazder Rahman, Gerhard W. Dueck, Anindita Banerjee
2011	—	`conf`	Two-Qubit Quantum Gates to Reduce the Quantum Cost of Reversible Circuit. ISMVL Md. Mazder Rahman, Anindita Banerjee, Gerhard W. Dueck, Anirban Pathak
2010	—	`conf`	ESOP-Based Toffoli Network Generation with Transformations. ISMVL Yasaman Sanaee, Gerhard W. Dueck
2010	C	`conf`	Synthesizing multiplier in reversible logic. DDECS Sebastian Offermann, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
2010	—	`conf`	Toffoli Gate Implementation Using the Billiard Ball Model. ISMVL Hadi Hosseini, Gerhard W. Dueck
2010	C	`conf`	Window optimization of reversible and quantum circuits. DDECS Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
2009	A	`conf`	Debugging of Toffoli networks. DATE Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
2009	J	`jnl`	Editorial. J. Multiple Valued Log. Soft Comput. Gerhard W. Dueck
2009	J	`jnl`	Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
2009	J	`jnl`	Exact Synthesis of Elementary Quantum Gate Circuits. J. Multiple Valued Log. Soft Comput. Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
2009	Misc	`conf`	Reversible Logic Synthesis with Output Permutation. VLSI Design Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler
2009	C	`conf`	Synthesizing Reversible Circuits for Irreversible Functions. DSD D. Michael Miller, Robert Wille, Gerhard W. Dueck
2008	—	`conf`	Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares. ISMVL Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
2008	—	`conf`	Pairwise decomposition of toffoli gates in a quantum circuit. ACM Great Lakes Symposium on VLSI Nathan O. Scott, Gerhard W. Dueck
2008	A	`conf`	Quantified Synthesis of Reversible Logic. DATE Robert Wille, Hoang Minh Le, Gerhard W. Dueck, Daniel Große
2008	J	`jnl`	Quantum Circuit Simplification and Level Compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller, Camille Negrevergne
2008	—	`conf`	RevLib: An Online Resource for Reversible Functions and Reversible Circuits. ISMVL Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler
2007	—	`conf`	Exact sat-based toffoli network synthesis. ACM Great Lakes Symposium on VLSI Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler
2007	J	`jnl`	Techniques for the synthesis of reversible Toffoli networks. ACM Trans. Design Autom. Electr. Syst. Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
2006	B	`conf`	Level Compaction in Quantum Circuits. IEEE Congress on Evolutionary Computation Dmitri Maslov, Gerhard W. Dueck
2006	J	`jnl`	Synthesis of Quantum Multiple-Valued Circuits. J. Multiple Valued Log. Soft Comput. D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck
2005	A	`conf`	Quantum Circuit Simplification Using Templates. DATE Dmitri Maslov, Christina Young, D. Michael Miller, Gerhard W. Dueck
2005	J	`jnl`	Synthesis of Fredkin-Toffoli reversible networks. IEEE Trans. Very Large Scale Integr. Syst. Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
2005	J	`jnl`	Toffoli network synthesis with templates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
2004	—	`conf`	A Synthesis Method for MVL Reversible Logi. ISMVL D. Michael Miller, Gerhard W. Dueck, Dmitri Maslov
2004	J	`jnl`	Reversible cascades with minimal garbage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dmitri Maslov, Gerhard W. Dueck
2003	A*	`conf`	A transformation based algorithm for reversible logic synthesis. DAC D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck
2003	A	`conf`	Fredkin/Toffoli Templates for Reversible Logic Synthesis. ICCAD Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
2003	—	`conf`	On the Size of Multiple-Valued Decision Diagrams. ISMVL D. Michael Miller, Gerhard W. Dueck
2003	—	`conf`	Simplification of Toffoli Networks via Templates. SBCCI Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
2001	J	`jnl`	On the number of generators for transeunt triangles. Discret. Appl. Math. Jon T. Butler, Gerhard W. Dueck, Svetlana N. Yanushkevich, Vlad P. Shmerko
2001	J	`jnl`	Using simulated annealing to construct extremal graphs. Discret. Math. Ping Wang, Gerhard W. Dueck, S. MacMillan
2000	J	`jnl`	Comments on "Sympathy: fast exact minimization of fixedpolarity Reed-Muller expansion for symmetric functions". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko, Svetlana N. Yanushkevich
2000	—	`conf`	Experiments on FPRM Expressions for Partially Symmetric Logic Functions. ISMVL Svetlana N. Yanushkevich, Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko
1999	—	`conf`	A Super Switch Algebra for Quantum Device Based Systems. ISMVL Gerhard W. Dueck, Mou Hu, Blair Fraser
1998	—	`conf`	Multiple-Valued Logic Minimization using Universal Literals and Cost Tables. ISMVL Blair Fraser, Gerhard W. Dueck
1994	—	`conf`	Multiple-Valued Logic Operations with Universal Literals. ISMVL Gerhard W. Dueck, Jon T. Butler
1992	—	`conf`	Direct Cover MVL Minimization with Cost-Tables. ISMVL Gerhard W. Dueck
1992	—	`conf`	Multiple-Valued Programmable Logic Array Minmization by Simulated Annealing. ISMVL Gerhard W. Dueck, Robert C. Earle, Parthasarathy P. Tirumalai, Jon T. Butler
1991	—	`conf`	On the Maximum Number of Implicants Needed to Cover a Multiple-Valued Logic Function Using Window Literals. ISMVL Gerhard W. Dueck, G. H. John van Rees
1990	—	`conf`	RCM-MVL: A Recursive Consensus MVL Minimization Algorithm. ISMVL Gerhard W. Dueck, D. Michael Miller