Gerald G. Pechanek

17 papers B 3Journal 5Unranked 9
YearRankTypeTitle / Venue / Authors
2017 — conf
An introduction to an array memory processor for application specific acceleration.
HPEC
Gerald G. Pechanek, Nikos Pitsianis
2003 J jnl
Indirect VLIW memory allocation for the ManArray multiprocessor DSP.
SIGARCH Comput. Archit. News
Nikos Pitsianis, Gerald G. Pechanek
2000 — conf
A 90k Gate "CLB" for Parallel Distributed Computing.
IPDPS Workshops
Bruce Schulman, Gerald G. Pechanek
2000 J jnl
A look inside the learning process of neural networks.
Complex.
Koen Bertels, Luc Neuberg, Stamatis Vassiliadis, Gerald G. Pechanek
2000 — conf
The ManArray( Embedded Processor Architecture.
EUROMICRO
Gerald G. Pechanek, Stamatis Vassiliadis
1999 J jnl
A neuro-emulator with embedded capabilities for generalized learning.
J. Syst. Archit.
Valentine C. Aikens II, José G. Delgado-Frias, Gerald G. Pechanek, Stamatis Vassiliadis
1999 — conf
ManArray Processor Interconnection Network: An Introduction.
Euro-Par
Gerald G. Pechanek, Stamatis Vassiliadis, Nikos Pitsianis
1998 — conf
The Sum-Absolute-Difference Motion Estimation Accelerato.
EUROMICRO
Stamatis Vassiliadis, Edwin A. Hakkennes, J. S. S. M. Wong, Gerald G. Pechanek
1996 — conf
A neuro-emulator with learning and virtual emulation capabilities.
ICNN
Valentine C. Aikens II, José G. Delgado-Frias, Steven M. Barber, Gerald G. Pechanek, Stamatis Vassiliadis
1996 — conf
Architectural simulation system for M.f.a.s.t.
Annual Simulation Symposium
Chris H. L. Moller, Gerald G. Pechanek
1995 — conf
A Neuro-Architecture with Embedded Learning.
Parallel and Distributed Computing and Systems
Valentine C. Aikens II, Steven M. Barber, José G. Delgado-Frias, Gerald G. Pechanek, Stamatis Vassiliadis
1995 B conf
MFAST: a single chip highly parallel image processing architecture.
ICIP
Gerald G. Pechanek, M. Stojancic, Stamatis Vassiliadis, C. John Glossner
1993 — conf
A massively parallel diagonal-fold array processor.
ASAP
Gerald G. Pechanek, José G. Delgado-Frias, Stamatis Vassiliadis
1993 J jnl
Spin: the Sequential Pipelined Neuroemulator.
Int. J. Artif. Intell. Tools
Stamatis Vassiliadis, Gerald G. Pechanek, José G. Delgado-Frias
1992 J jnl
Digital neural emulators using tree accumulation and communication structures.
IEEE Trans. Neural Networks
Gerald G. Pechanek, Stamatis Vassiliadis, José G. Delgado-Frias
1991 B conf
AI in multimedia (panel session).
ICTAI
Nikolaos G. Bourbakis, Robin Williams, Forouzan Golshani, Myron Flickner, Ted Laliotis, Sukhan Lee, José G. Delgado-Frias, Dan Hammerstrom, Cris Koutsougeras, Gerald G. Pechanek, Benjamin W. Wah, John Yen, Farokh B. Bastani, Tom Cooper, Karan Harbison-Briggs, Rudy Lauber, Alun D. Preece, Imran A. Zualkernan, W. T. Tsai, Daniel E. Cooke, Martin S. Feather, Stephen Fickas, N. Minsky, Peter G. Selfridge, Douglas Smith
1991 B conf
SPIN: a sequential pipelined neurocomputer.
ICTAI
Stamatis Vassiliadis, Gerald G. Pechanek, José G. Delgado-Frias