Georges G. E. Gielen

443 papers A* 25A 82B 17C 27Misc 4Journal 151Unranked 133

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A Generalized Constraint Learning and Transfer Methodology with Net-First Graph Neural Network and Selective Topological Search for Hierarchical Analog / Mixed-Signal Circuit Layout Synthesis. ACM Trans. Design Autom. Electr. Syst. Kaichang Chen, Georges G. E. Gielen
2026	J	`jnl`	An Analytical Model for Performance-Carbon Co-Optimization of Edge AI Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jiacong Sun, Xiaoling Yi, Arne Symons, Georges G. E. Gielen, Lieven Eeckhout, Marian Verhelst
2026	J	`jnl`	AnaCraft: Duel-Play Probabilistic-Model-Based Reinforcement Learning for Sample-Efficient PVT-Robust Analog Circuit Sizing Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mohsen Ahmadzadeh, Jan Lappas, Norbert Wehn, Georges G. E. Gielen
2026	J	`jnl`	SunPar: An Analytical Design Space Exploration Framework Modeling Performance Uncertainty in Sparse AI Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jiacong Sun, Man Shi, Mahesh Subedar, Georges G. E. Gielen, Marian Verhelst
2025	A	`conf`	(Invited Paper) AnaFlow: Agentic LLM-based Workflow for Reasoning-Driven Explainable and Sample-Efficient Analog Circuit Sizing. ICCAD Mohsen Ahmadzadeh, Kaichang Chen, Georges G. E. Gielen
2025	J	`jnl`	A 376-μW per-Channel, Drift-Tolerant Translocation Recording Frontend With Event Detection for Nanopore Sensor Arrays. IEEE J. Solid State Circuits Aurojyoti Das, Qiuyang Lin, Yixiong Hu, Wim Sijbers, Eric Beamish, Chris Van Hoof, Georges G. E. Gielen, Nick Van Helleputte
2025	J	`jnl`	A Brief 20-Year History and Future Perspectives on Sizing and Layout Synthesis of Analog/RF ICs. IEEE Des. Test Georges G. E. Gielen
2025	—	`conf`	A Carrier-Energy-Based Compact Model for Hot-Carrier Degradation Implemented in Verilog-A. IRPS Dishant Sangani, Michiel Vandemaele, Stanislav Tyaginov, Erik Bury, Ben Kaczer, Georges G. E. Gielen
2025	—	`conf`	A Comparative Study of Switch-Mode and Constant-Current Methods for High-Efficiency Neural Stimulation. SMACD Sergio Massaioli, Georges G. E. Gielen
2025	C	`conf`	A Digital Jitter Correction Technique For High-Speed ADC-Based Communication Links. ISCAS Tim Borremans, Jun Feng, Jonah Van Assche, Georges G. E. Gielen, Filip Tavernier
2025	J	`jnl`	A Fully-Integrated Many-Electrodes Pulsed-Voltage Control Architecture for Arbitrary-Waveform Neural Stimulation With High Energy Efficiency. IEEE Trans. Circuits Syst. I Regul. Pap. Sergio Massaioli, Marco Francesco Carlino, Georges G. E. Gielen
2025	J	`jnl`	AnaFlow: Agentic LLM-based Workflow for Reasoning-Driven Explainable and Sample-Efficient Analog Circuit Sizing. CoRR Mohsen Ahmadzadeh, Kaichang Chen, Georges G. E. Gielen
2025	C	`conf`	CIPL: A Fast and Low-Power Level Shifter for Wide-Range Voltage Conversion. ISCAS Weijie Jiang, Xinfa Zheng, Jiacong Sun, Georges G. E. Gielen, Marian Verhelst, Wim Dehaene
2025	C	`conf`	DERMIS: Toward a Fully-Integrated Large-Area High-Resolution Tactile Slip Sensing Solution. ISCAS Mark Daniel Alea, Maria Atalaia Rosa, Sara Farfalha, Kris Myny, Georges G. E. Gielen
2025	J	`jnl`	Dynamic Sub-Array Selection-Based Energy-Efficient Localization and Tracking Method to Power Implanted Medical Devices in Scattering Heterogenous Media Employing Ultrasound. IEEE Trans. Biomed. Circuits Syst. Anirudh Kumar Parag, Bogdan C. Raducanu, Oguz Kaan Erden, Stefano Stanzione, Fabian Beutel, Chinmay Pendse, Chris Van Hoof, Nick Van Helleputte, Georges G. E. Gielen
2025	B	`conf`	European Test Symposium Teams: an Anniversary Snapshot. ETS Maksim Jenihhin, Jaan Raik, Artur Jutman, Natalia Cherezova, Raimund Ubar, Liviu Miclea, Szilárd Enyedi, I. Stefan, Ovidiu Stan, Cosmina Corches, Z. Peng, Petru Eles, Rolf Drechsler, S. Eggersglüß, Görschwin Fey, Andreas Glowatz, Daniel Tille, Georges G. E. Gielen, Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, P.-Y. Chuang, Erik Jan Marinissen, Giorgio Di Natale, M. Barragan, Paolo Maistri, S. Mir, Vatajelu I. Vatajelu, Paolo Bernardi, S. Di Carlo, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante, Haralampos-G. Stratigopoulos, M. K. Michael, Stelios Neophytou, Stavros Hadjitheophanous, Kyriakos Christou, M. Skitsas, Alberto Bosio, Bastien Deveautour, P. Girard, Marcello Traiola, Arnaud Virazel, F. Fernandes Dos Santos, Angeliki Kritikakou, Gioele Casagranda, Marzio Vallero, Flavio Vella, Paolo Rech, Letícia Maria Bolzani Poehls, Milos Krstic, Marko S. Andjelkovic, F. Vargas, Grigor Tshagharyan, Gurgen Harutyunyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Mottaqiallah Taouil, Moritz Fieback, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, Abhijit Chatterjee, A. Saha, Suhasini Komarraju, K. Ma, Chandramouli N. Amarnath, Mehdi Baradaran Tahoori, Mahta Mayahinia, Maryam Rajabalipanah, Katayoon Basharkhah, N. Nosrati, Zahra Jahanpeima, Zain Navabi, Hans-Joachim Wunderlich, Sybille Hellebrand
2025	—	`book`	Event-Driven Circuit Architectures for Scalable and Adaptive Sensor Readout Jonah Van Assche, Georges G. E. Gielen
2025	J	`jnl`	FREYA: A 0.023-mm²/Channel, 20.8- μW/Channel, Event-Driven 8-Channel SoC for Spiking End-to-End Sensing of Time-Sparse Biosignals. IEEE Trans. Circuits Syst. I Regul. Pap. Jonah Van Assche, Charlotte Frenkel, Ali Safa, Georges G. E. Gielen
2025	A*	`conf`	Graph-Guided Transfer Learning to Boost the Efficiency of System-Level Optimization of Analog/Mixed-Signal Circuits. DAC Jiaqi Wang, Georges G. E. Gielen
2025	J	`jnl`	Guest Editorial TCAS-I Special Issue on the ESSERC 2024 Conference. IEEE Trans. Circuits Syst. I Regul. Pap. Georges G. E. Gielen, Jan Craninckx, Hongyang Jia
2025	—	`conf`	Hybrid AI-Optimization Method for Latent Defect Detection Through Test Transistor Insertion in Analog Circuits. SMACD Sankhya Bhattacharya, Georges G. E. Gielen
2025	—	`conf`	Spiking Liquid Time-Constant Networks (sLTC): An Energy-Efficient and Adaptive Neuromorphic Approach. ICECS Karen Vanhalle, Georges G. E. Gielen
2025	—	`conf`	Towards a Computationally Efficient Verilog-A Defect-Centric BTI Compact Model for Circuit Aging Simulations. IRPS Dishant Sangani, Dieter Claes, Pieter Weckx, Ben Kaczer, Georges G. E. Gielen
2024	—	`conf`	A 3072-Channel Neural Readout IC with Multiplexed Two-Step Incremental-SAR Conversion and Bulk-DAC-Based EDO Compensation in 22nm FDSOI. VLSI Technology and Circuits Xiaohua Huang, Xiaolin Yang, Andrea Lodi, Chris Van Hoof, Georges G. E. Gielen, Carolina Mora Lopez
2024	C	`conf`	A 70dB SNDR 20MHz-BW VCO-Based CT Sturdy MASH Delta-Sigma Modulator with Robust Quantization Error Extraction. ISCAS Xinpeng Gui, Xinfa Zheng, Haigang Feng, Georges G. E. Gielen, Zhihua Wang, Xinpeng Xing
2024	J	`jnl`	A Fingertip-Mimicking 12$\times$16 200 $\mu$m-Resolution e-Skin Taxel Readout Chip With Per-Taxel Spiking Readout and Embedded Receptive Field Processing. IEEE Trans. Biomed. Circuits Syst. Mark Daniel Alea, Ali Safa, Flavio Giacomozzi, Andrea Adami, Inci Rüya Temel, Maria Atalaia Rosa, Leandro Lorenzelli, Georges G. E. Gielen
2024	J	`jnl`	Analysis and Design of a 10.4-ENOB 0.92-5.38-μW Event-Driven Level-Crossing ADC With Adaptive Clocking for Time-Sparse Edge Applications. IEEE J. Solid State Circuits Jonah Van Assche, Georges G. E. Gielen
2024	J	`jnl`	Brain Feature Extraction With an Artifact-Tolerant Multiplexed Time-Encoding Neural Frontend for True Real-Time Closed-Loop Neuromodulation. IEEE Trans. Biomed. Circuits Syst. Marco Francesco Carlino, Georges G. E. Gielen
2024	—	`conf`	Possible Origins, Identification, and Screening of Silent Data Corruption in Data Centers. IRPS Dishant Sangani, Ben Kaczer, Pieter Weckx, Philippe J. Roussel, Subrat Mishra, Erik Jan Marinissen, Georges G. E. Gielen
2024	J	`jnl`	STDP-Driven Development of Attention-Based People Detection in Spiking Neural Networks. IEEE Trans. Cogn. Dev. Syst. Ali Safa, Ilja Ocket, André Bourdoux, Hichem Sahli, Francky Catthoor, Georges G. E. Gielen
2024	A	`conf`	Self-Learning and Transfer Across Topologies of Constraints for Analog / Mixed-Signal Circuit Layout Synthesis. DATE Kaichang Chen, Georges G. E. Gielen
2024	B	`conf`	Silent Data Corruption: Test or Reliability Problem? ETS Erik Jan Marinissen, Harish Dattatraya Dixit, Ronald Shawn Blanton, Aaron Kuo, Wei Li, Subhasish Mitra, Chris Nigh, Ruben Purdy, Ben Kaczer, Dishant Sangani, Pieter Weckx, Philippe J. Roussel, Georges G. E. Gielen
2024	—	`conf`	Statistical Characterization of Off-State Stress Degradation in Planar HKMG nFETs Using Device Arrays. IRPS Pablo Saraza-Canflanca, Dishant Sangani, Javier Diaz-Fortuny, Stanislav Tyaginov, Georges G. E. Gielen, Erik Bury, Ben Kaczer
2024	—	`conf`	Towards Chip-in-the-loop Spiking Neural Network Training via Metropolis-Hastings Sampling. NICE Ali Safa, Vikrant Jaltare, Samira Sebt, Kameron Gano, Johannes Leugering, Georges G. E. Gielen, Gert Cauwenberghs
2024	J	`jnl`	Towards Chip-in-the-loop Spiking Neural Network Training via Metropolis-Hastings Sampling. CoRR Ali Safa, Vikrant Jaltare, Samira Sebt, Kameron Gano, Johannes Leugering, Georges G. E. Gielen, Gert Cauwenberghs
2024	A*	`conf`	Using Probabilistic Model Rollouts to Boost the Sample Efficiency of Reinforcement Learning for Automated Analog Circuit Sizing. DAC Mohsen Ahmadzadeh, Georges G. E. Gielen
2023	—	`conf`	A 384-Channel Online-Spike-Sorting IC Using Unsupervised Geo-OSort Clustering and Achieving 0.0013mm ISSCC Yingping Chen, Bernardo Tacca, Yunzhu Chen, Dwaipayan Biswas, Georges G. E. Gielen, Francky Catthoor, Marian Verhelst, Carolina Mora Lopez
2023	—	`conf`	A Fingertip-Mimicking 12×16 200μm-Resolution e-skin Taxel Readout Chip with per-Taxel Spiking Readout and Embedded Receptive Field Processing. VLSI Technology and Circuits Mark Daniel Alea, Ali Safa, Flavio Giacomozzi, Andrea Adami, Inci Rüya Temel, Leandro Lorenzelli, Georges G. E. Gielen
2023	—	`conf`	Active Inference in Hebbian Learning Networks. IWAI Ali Safa, Tim Verbelen, Lars Keuninckx, Ilja Ocket, André Bourdoux, Francky Catthoor, Georges G. E. Gielen, Gert Cauwenberghs
2023	J	`jnl`	Active Inference in Hebbian Learning Networks. CoRR Ali Safa, Tim Verbelen, Lars Keuninckx, Ilja Ocket, André Bourdoux, Francky Catthoor, Georges G. E. Gielen, Gert Cauwenberghs
2023	J	`jnl`	An Online-Spike-Sorting IC Using Unsupervised Geometry-Aware OSort Clustering for Efficient Embedded Neural-Signal Processing. IEEE J. Solid State Circuits Yingping Chen, Bernardo Tacca, Yunzhu Chen, Dwaipayan Biswas, Georges G. E. Gielen, Francky Catthoor, Marian Verhelst, Carolina Mora Lopez
2023	—	`conf`	Analog synthesis 3.0: AI/ML to synthesize and test analog ICs: hope or hype ? MLCAD Georges G. E. Gielen
2023	J	`jnl`	Boosting Latent Defect Coverage in Automotive Mixed-Signal ICs Using SVM Classifiers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nektar Xama, Jhon Gomez, Wim Dobbelaere, Ronny Vanhooren, Anthony Coyette, Georges G. E. Gielen
2023	J	`jnl`	Delay Cell for Highly-Linear Current-Controlled Oscillator-Based Analog-to-Digital Conversion. IEEE Trans. Circuits Syst. II Express Briefs Leidy Mabel Alvero-Gonzalez, Georges G. E. Gielen, Eric Gutierrez
2023	—	`conf`	Effective and Efficient Test and Diagnosis Pattern Generation for Many Inter-Die Interconnects in Chiplet-Based Packages. 3DIC Po-Yao Chuang, Francesco Lorenzelli, Sreejit Chakravarty, Slimane Boutobza, Cheng-Wen Wu, Georges G. E. Gielen, Erik Jan Marinissen
2023	Misc	`conf`	Effective and Efficient Testing of Large Numbers of Inter-Die Interconnects in Chiplet-Based Multi-Die Packages. VTS Po-Yao Chuang, Francesco Lorenzelli, Sreejit Chakravarty, Cheng-Wen Wu, Georges G. E. Gielen, Erik Jan Marinissen
2023	A	`conf`	End-to-End Optimization of High-Density e-Skin Design: From Spiking Taxel Readout to Texture Classification. DATE Jiaqi Wang, Mark Daniel Alea, Jonah Van Assche, Georges G. E. Gielen
2023	—	`conf`	Exploring Information-Theoretic Criteria to Accelerate the Tuning of Neuromorphic Level-Crossing ADCs. NICE Ali Safa, Jonah Van Assche, Charlotte Frenkel, André Bourdoux, Francky Catthoor, Georges G. E. Gielen
2023	—	`conf`	From sensor to inference: end-to-end chip design for wearable and implantable biomedical applications. BioCAS Jonah Van Assche, Marco Francesco Carlino, Mark Daniel Alea, Sergio Massaioli, Georges G. E. Gielen
2023	A*	`conf`	Fusing Event-based Camera and Radar for SLAM Using Spiking Neural Networks with Continual STDP Learning. ICRA Ali Safa, Tim Verbelen, Ilja Ocket, André Bourdoux, Hichem Sahli, Francky Catthoor, Georges G. E. Gielen
2023	J	`jnl`	High-Throughput Nanopore-FET Array Readout IC With 5-MHz Bandwidth and Background Offset/Drift Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. Aurojyoti Das, Qiuyang Lin, Sybren Santermans, Lijun Liu, Chris Van Hoof, Georges G. E. Gielen, Nick Van Helleputte
2023	B	`conf`	High-coverage analog IP block test generation methodology using low-cost signal generation and output response analysis. ETS Jhon Gomez, Nektar Xama, Anthony Coyette, Ronny Vanhooren, Wim Dobbelaere, Georges G. E. Gielen
2023	—	`conf`	Highly-Digital 0.0018-mm BioCAS Marco Francesco Carlino, Sergio Massaioli, Georges G. E. Gielen
2023	J	`jnl`	Improving the Accuracy of Spiking Neural Networks for Radar Gesture Recognition Through Preprocessing. IEEE Trans. Neural Networks Learn. Syst. Ali Safa, Federico Corradi, Lars Keuninckx, Ilja Ocket, André Bourdoux, Francky Catthoor, Georges G. E. Gielen
2023	—	`conf`	Neuromorphic computing in the edge: merging cyber and physical. IWASI Georges G. E. Gielen
2023	B	`conf`	Study of Transistor Metrics for Room-Temperature Screening of Single Electron Transistors for Silicon Spin Qubit Applications. ETS Francesco Lorenzelli, Asser Elsayed, Clement Godfrin, Alexander Grill, Stefan Kubicek, Ruoyu Li, Michele Stucchi, Danny Wan, Kristiaan De Greve, Erik Jan Marinissen, Georges G. E. Gielen
2023	—	`conf`	SupportHDC: Hyperdimensional Computing with Scalable Hypervector Sparsity. NICE Ali Safa, Ilja Ocket, Francky Catthoor, Georges G. E. Gielen
2023	—	`conf`	The Role of Mobility Degradation in the BTI-Induced RO Aging in a 28-nm Bulk CMOS Technology: (Student paper). IRPS Dishant Sangani, Javier Diaz-Fortuny, Erik Bury, Ben Kaczer, Georges G. E. Gielen
2023	A	`conf`	Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures. ITC Francesco Lorenzelli, Asser Elsayed, Clement Godfrin, Alexander Grill, Stefan Kubicek, Ruoyu Li, Michele Stucchi, Danny Wan, Kristiaan De Greve, Erik Jan Marinissen, Georges G. E. Gielen
2022	—	`conf`	A 10.4-ENOB 0.92-5.38 μW Event-Driven Level-Crossing ADC with Adaptive Clocking for Time-Sparse Edge Applications. ESSCIRC Jonah Van Assche, Georges G. E. Gielen
2022	—	`conf`	A 256-Channel Actively-Multiplexed µECoG Implant with Column-Parallel Incremental ΔΣ ADCs Employing Bulk-DACs in 22-nm FDSOI Technology. ISSCC Xiaohua Huang, Horacio Londoño-Ramírez, Marco Ballini, Chris Van Hoof, Jan Genoe, Sebastian Haesler, Georges G. E. Gielen, Nick Van Helleputte, Carolina Mora Lopez
2022	J	`jnl`	A 96.9-dB-Resolution 109-μW Second-Order Robust Closed-Loop VCO-Based Sensor Interface for Multiplexed Single-Ended Resistance Readout in 180-nm CMOS. IEEE J. Solid State Circuits Elisa Sacco, Johan Vergauwen, Georges G. E. Gielen
2022	J	`jnl`	A Co-Simulation Methodology for the Design of Integrated Silicon Spin Qubits With Their Control/Readout Cryo-CMOS Electronics. IEEE J. Emerg. Sel. Topics Circuits Syst. Benjamin Gys, Rohith Acharya, Steven Van Winckel, Kristiaan De Greve, Georges G. E. Gielen, Francky Catthoor
2022	J	`jnl`	A Compact, Low-Power Analog Front-End With Event-Driven Input Biasing for High-Density Neural Recording in 22-nm FDSOI. IEEE Trans. Circuits Syst. II Express Briefs Xiaohua Huang, Marco Ballini, Shiwei Wang, Beatrice Miccoli, Chris Van Hoof, Georges G. E. Gielen, Jan Craninckx, Nick Van Helleputte, Carolina Mora Lopez
2022	—	`conf`	A servo-loop-free charge sharing technique to mitigate electrode offsets in biomedical multiplexed interfaces. ICECS 2022 Marco Francesco Carlino, Georges G. E. Gielen
2022	J	`jnl`	Actively Multiplexed μECoG Brain Implant System With Incremental-ΔΣ ADCs Employing Bulk-DACs. IEEE J. Solid State Circuits Xiaohua Huang, Horacio Londoño-Ramírez, Marco Ballini, Chris Van Hoof, Jan Genoe, Sebastian Haesler, Georges G. E. Gielen, Nick Van Helleputte, Carolina Mora Lopez
2022	—	`conf`	An 8-b 8-GS/s Time-Interleaved SAR ADC With Foreground Offset Calibration in 28nm CMOS. APCCAS Zhanpeng Yang, Xinpeng Xing, Xinfa Zheng, Haigang Feng, Hongyan Fu, Georges G. E. Gielen
2022	J	`jnl`	Continuously Learning to Detect People on the Fly: A Bio-inspired Visual System for Drones. CoRR Ali Safa, Ilja Ocket, André Bourdoux, Hichem Sahli, Francky Catthoor, Georges G. E. Gielen
2022	J	`jnl`	DDtM: Increasing Latent Defect Detection in Analog/Mixed-Signal ICs Using the Difference in Distance to Mean Value. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jhon Gomez, Nektar Xama, Anthony Coyette, Ronny Vanhooren, Wim Dobbelaere, Georges G. E. Gielen
2022	A	`conf`	EffiCSense: an Architectural Pathfinding Framework for Energy-Constrained Sensor Applications. DATE Jonah Van Assche, Ruben Helsen, Georges G. E. Gielen
2022	B	`conf`	Event Camera Data Classification Using Spiking Networks with Spike-Timing-Dependent Plasticity. IJCNN Ali Safa, Ilja Ocket, André Bourdoux, Hichem Sahli, Francky Catthoor, Georges G. E. Gielen
2022	—	`conf`	Exploring Cross-fusion and Curriculum Learning for Multi-modal Human Detection on Drones. DroneSE/RAPIDO@HiPEAC Ali Safa, Ilja Ocket, Francky Catthoor, Georges G. E. Gielen
2022	J	`jnl`	Fail-Safe Human Detection for Drones Using a Multi-Modal Curriculum Learning Approach. IEEE Robotics Autom. Lett. Ali Safa, Tim Verbelen, Ilja Ocket, André Bourdoux, Francky Catthoor, Georges G. E. Gielen
2022	J	`jnl`	Fusing Event-based Camera and Radar for SLAM Using Spiking Neural Networks with Continual STDP Learning. CoRR Ali Safa, Tim Verbelen, Ilja Ocket, André Bourdoux, Hichem Sahli, Francky Catthoor, Georges G. E. Gielen
2022	—	`conf`	Learning to Encode Vision on the Fly in Unknown Environments: A Continual Learning SLAM Approach for Drones. SSRR Ali Safa, Tim Verbelen, Ilja Ocket, André Bourdoux, Hichem Sahli, Francky Catthoor, Georges G. E. Gielen
2022	J	`jnl`	Learning to SLAM on the Fly in Unknown Environments: A Continual Learning Approach for Drones in Visually Ambiguous Scenes. CoRR Ali Safa, Tim Verbelen, Ilja Ocket, André Bourdoux, Hichem Sahli, Francky Catthoor, Georges G. E. Gielen
2022	—	`conf`	Low Power and High Speed Designs of CIC Filter for Sigma-Delta ADCs. APCCAS Zhikun He, Xinpeng Xing, Xinfa Zheng, Haigang Feng, Hongyan Fu, Georges G. E. Gielen
2022	J	`jnl`	Methodology for Readout and Ring Oscillator Optimization Toward Energy-Efficient VCO-Based ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. Jonas Borgmans, Elisa Sacco, Pieter Rombouts, Georges G. E. Gielen
2022	J	`jnl`	Neuromorphic Near-Sensor Computing: From Event-Based Sensing to Edge Learning. IEEE Micro Ali Safa, Jonah Van Assche, Mark Daniel Alea, Francky Catthoor, Georges G. E. Gielen
2022	—	`conf`	Power-Efficient and Accurate Texture Sensing Using Spiking Readouts for High-Density e-Skins. BioCAS Mark Daniel Alea, Ali Safa, Jonah Van Assche, Georges G. E. Gielen
2022	—	`conf`	Scalable 1.4 μW cryo-CMOS SP4T multiplexer operating at 10 mK for high-fidelity superconducting qubit measurements. VLSI Technology and Circuits Rohith Acharya, Anton Potocnik, Steven Brebels, Alexander Grill, Jeroen Verjauw, Tsvetan Ivanov, Daniel Perez Lozano, Danny Wan, Fahd A. Mohiyaddin, Jacques Van Damme, A. M. Vadiraj, Massimo Mongillo, Georges G. E. Gielen, Francky Catthoor, Jan Craninckx, Iuliana P. Radu, Bogdan Govoreanu
2021	J	`jnl`	A 0-dB STF-Peaking 85-MHz BW 74.4-dB SNDR CT ΔΣ ADC With Unary-Approximating DAC Calibration in 28-nm CMOS. IEEE J. Solid State Circuits Hui Liu, Xinpeng Xing, Georges G. E. Gielen
2021	J	`jnl`	A Low-Complexity Radar Detector Outperforming OS-CFAR for Indoor Drone Obstacle Avoidance. CoRR Ali Safa, Tim Verbelen, Lars Keuninckx, Ilja Ocket, Matthias Hartmann, André Bourdoux, Francky Catthoor, Georges G. E. Gielen
2021	J	`jnl`	A Low-Complexity Radar Detector Outperforming OS-CFAR for Indoor Drone Obstacle Avoidance. IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens. Ali Safa, Tim Verbelen, Lars Keuninckx, Ilja Ocket, Matthias Hartmann, André Bourdoux, Francky Catthoor, Georges G. E. Gielen
2021	J	`jnl`	Analysis and Comparison of Readout Architectures and Analog-to-Digital Converters for 3D-Stacked CMOS Image Sensors. IEEE Trans. Circuits Syst. I Regul. Pap. Nicolas Callens, Georges G. E. Gielen
2021	—	`conf`	Circuit Model for the Efficient Co-Simulation of Spin Qubits and their Control & Readout Circuitry. ESSCIRC Benjamin Gys, Fahd A. Mohiyaddin, Rohith Acharya, Roy Li, Kristiaan De Greve, Georges G. E. Gielen, Bogdan Govoreanu, Iuliana P. Radu, Francky Catthoor
2021	—	`conf`	Circuit Model for the Efficient Co-Simulation of Spin Qubits and their Control & Readout Circuitry. ESSDERC Benjamin Gys, Fahd A. Mohiyaddin, Rohith Acharya, Roy Li, Kristiaan De Greve, Georges G. E. Gielen, Bogdan Govoreanu, Iuliana P. Radu, Francky Catthoor
2021	A	`conf`	Circuit models for the co-simulation of superconducting quantum computing systems. DATE Rohith Acharya, Fahd A. Mohiyaddin, Anton Potocnik, Kristiaan De Greve, Bogdan Govoreanu, Iuliana P. Radu, Georges G. E. Gielen, Francky Catthoor
2021	J	`jnl`	ConvSNN: A surrogate gradient spiking neural framework for radar gesture recognition. Softw. Impacts Ali Safa, Francky Catthoor, Georges G. E. Gielen
2021	J	`jnl`	Fail-Safe Human Detection for Drones Using a Multi-Modal Curriculum Learning Approach. CoRR Ali Safa, Tim Verbelen, Ilja Ocket, André Bourdoux, Francky Catthoor, Georges G. E. Gielen
2021	J	`jnl`	Learning Event-based Spatio-Temporal Feature Descriptors via Local Synaptic Plasticity: A Biologically-realistic Perspective of Computer Vision. CoRR Ali Safa, Hichem Sahli, André Bourdoux, Ilja Ocket, Francky Catthoor, Georges G. E. Gielen
2021	—	`conf`	Power-efficient VCO-based ADCs for Wireless Communication Systems. ISOCC Xinpeng Xing, Xueqian Shang, Senji Liu, Xinfa Zheng, Georges G. E. Gielen
2021	J	`jnl`	Quantum Accelerator Stack: A Research Roadmap. CoRR Koen Bertels, Aritra Sarkar, Anna M. Krol, Ravish Budhrani, J. Samadi, E. Geoffroy, J. Matos, R. Abreu, Georges G. E. Gielen, Imran Ashraf
2020	J	`jnl`	A 16.1-bit Resolution 0.064-mm IEEE J. Solid State Circuits Elisa Sacco, Johan Vergauwen, Georges G. E. Gielen
2020	B	`conf`	Avoiding Mixed-Signal Field Returns by Outlier Detection of Hard-to-Detect Defects based on Multivariate Statistics. ETS Nektar Xama, Jakob Raymaekers, Martin Andraud, Jhon Gomez, Wim Dobbelaere, Ronny Vanhooren, Anthony Coyette, Georges G. E. Gielen
2020	J	`jnl`	Efficient Offline Outer/Inner DAC Mismatch Calibration in Wideband ΔΣ ADCs. IEEE Trans. Circuits Syst. Hui Liu, Pieter Rombouts, Georges G. E. Gielen
2020	—	`conf`	Improving the EMI Robustness of Feedback-based Time-Encoding Readout Architectures for Resistive Sensor Interfaces. ICECS Elisa Sacco, Johan Vergauwen, Georges G. E. Gielen
2020	B	`conf`	Latent Defect Screening with Visually-Enhanced Dynamic Part Average Testing. ETS Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, Nektar Xama, Jhon Gomez, Georges G. E. Gielen
2020	J	`jnl`	Machine Learning-based Defect Coverage Boosting of Analog Circuits under Measurement Variations. ACM Trans. Design Autom. Electr. Syst. Nektar Xama, Martin Andraud, Jhon Gomez, Baris Esen, Wim Dobbelaere, Ronny Vanhooren, Anthony Coyette, Georges G. E. Gielen
2020	Misc	`conf`	Pinhole Latent Defect Modeling and Simulation for Defect-Oriented Analog/Mixed-Signal Testing. VTS Jhon Gomez, Nektar Xama, Anthony Coyette, Ronny Vanhooren, Wim Dobbelaere, Georges G. E. Gielen
2020	J	`jnl`	Power Efficiency Comparison of Event-Driven and Fixed-Rate Signal Conversion and Compression for Biomedical Applications. IEEE Trans. Biomed. Circuits Syst. Jonah Van Assche, Georges G. E. Gielen
2020	A	`conf`	Quick Analyses for Improving Reliability and Functional Safety of Mixed-Signal ICs. ITC Stephen Sunter, Michal Wolinski, Anthony Coyette, Ronny Vanhooren, Wim Dobbelaere, Nektar Xama, Jhon Gomez, Georges G. E. Gielen
2019	—	`conf`	A 16.1-b ENOB 0.064mm A-SSCC Elisa Sacco, Johan Vergauwen, Georges G. E. Gielen
2019	J	`jnl`	A Robust BBPLL-Based 0.18- $\mu$ m CMOS Resistive Sensor Interface With High Drift Resilience Over a -40 °C-175 °C Temperature Range. IEEE J. Solid State Circuits Jorge Marin, Elisa Sacco, Johan Vergauwen, Georges G. E. Gielen
2019	J	`jnl`	An 85-MHz-BW ASAR-Assisted CT 4-0 MASH $\Delta\Sigma$ Modulator With Background Half-Range Dithering-Based DAC Calibration in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Hui Liu, Xinpeng Xing, Georges G. E. Gielen
2019	A	`conf`	Applying Vstress and defect activation coverage to produce zero-defect mixed-signal automotive ICs. ITC Wim Dobbelaere, Frederik Colle, Anthony Coyette, Ronny Vanhooren, Nektar Xama, Jhon Gomez, Georges G. E. Gielen
2019	—	`conf`	Architectural Analysis of a Novel Closed-Loop VCO-Based 1-1 Sturdy MASH Sensor-to-Digital Converter. SMACD Elisa Sacco, Johan Vergauwen, Georges G. E. Gielen
2019	—	`conf`	From Open-Loop to Closed-Loop Single-VCO-Based Sensor-to-Digital Converter Architectures: theoretical analysis and comparison. IWASI Elisa Sacco, Johan Vergauwen, Georges G. E. Gielen
2019	J	`jnl`	Performance Limitation Analysis of Highly-Digital Time-Based Closed-Loop Sensor-to-Digital Converter Architectures. IEEE Trans. Circuits Syst. II Express Briefs Elisa Sacco, Jorge Marin, Johan Vergauwen, Georges G. E. Gielen
2019	A	`conf`	Review of Methodologies for Pre- and Post-Silicon Analog Verification in Mixed-Signal SOCs. DATE Georges G. E. Gielen, Nektar Xama, Karthik Ganesan, Subhasish Mitra
2019	—	`conf`	The fantastic voyage towards ultra-miniaturized sensing circuits. IWASI Georges G. E. Gielen
2019	J	`jnl`	Understanding the Impact of Time-Dependent Random Variability on Analog ICs: From Single Transistor Measurements to Circuit Simulations. IEEE Trans. Very Large Scale Integr. Syst. Marko Simicic, Pieter Weckx, Bertrand Parvais, Philippe Roussel, Ben Kaczer, Georges G. E. Gielen
2018	J	`jnl`	A 0.18-µm CMOS Image Sensor With Phase-Delay-Counting and Oversampling Dual-Slope Integrating Column ADCs Achieving 1e IEEE J. Solid State Circuits Ha Le-Thai, Genis Chapinal, Tomas Geurts, Georges G. E. Gielen
2018	—	`conf`	A Single-Temperature-Calibration 0.18-µm CMOS Time-Based Resistive Sensor Interface with Low Drift over a -40°C to 175°C Temperature Range. ESSCIRC Jorge Marin, Elisa Sacco, Johan Vergauwen, Georges G. E. Gielen
2018	J	`jnl`	ADAGE: Automatic DfT-Assisted Generation of Test Stimuli for Mixed- Signal Integrated Circuits. IEEE Des. Test Anthony Coyette, Baris Esen, Nektar Xama, Georges G. E. Gielen, Wim Dobbelaere, Ronny Vanhooren
2018	—	`conf`	An 85MHz-BW 68.5dB-SNDR ASAR-assisted CT 4-0 MASH ΔΣ modulator with half-range dithering-based DAC calibration in 28nm CMOS. CICC Hui Liu, Xinpeng Xing, Georges G. E. Gielen
2018	J	`jnl`	An Automated Low-Cost Analog and Mixed-Signal DfT Method Using Testing Diodes. IEEE Des. Test Baris Esen, Anthony Coyette, Nektar Xama, Georges G. E. Gielen, Wim Dobbelaere, Ronny Vanhooren
2018	—	`conf`	Controlled-Oscillator Optimization for Highly-Digital CMOS Time-Based Sensor-to-Digital Converter Architectures. SMACD Elisa Sacco, Jorge Marin, Johan Vergauwen, Georges G. E. Gielen
2018	J	`jnl`	Generalized mode solver for plasmonic transmission lines embedded in layered media based on the Method of Moments. Comput. Phys. Commun. Mai O. Sallam, Guy A. E. Vandenbosch, Georges G. E. Gielen, Ezzeldin A. Soliman
2018	—	`conf`	Improving the robustness and drift resilience of CMOS BBPLL-based time-based sensor interfaces. ICECS Georges G. E. Gielen, Jorge Marin, Elisa Sacco
2018	C	`conf`	Methodology Towards Sub-ppm Testing of Analog and Mixed-Signal ICs for Cyber-Physical Systems. ISCAS Georges G. E. Gielen, Baris Esen, Wim Dobbelaere, Ronny Vanhooren, Anthony Coyette, Nektar Xama
2017	J	`jnl`	A 0.6-V, 0.015-mm IEEE J. Solid State Circuits Rachit Mohan, Samira Zaliasl, Georges G. E. Gielen, Chris Van Hoof, Refet Firat Yazicioglu, Nick Van Helleputte
2017	—	`conf`	A power-efficient reconfigurable two-step VCO-based ADC for software-defined radio. ASICON Xinpeng Xing, Peng Zhu, Hui Liu, Wei Wang, Georges G. E. Gielen
2017	B	`conf`	A very low cost and highly parallel DfT method for analog and mixed-signal circuits. ETS Baris Esen, Anthony Coyette, Nektar Xama, Wim Dobbelaere, Ronny Vanhooren, Georges G. E. Gielen
2017	—	`conf`	Analysis and modeling of drift-resilient time-based integrated resistive sensor interfaces. IWASI Jorge Marin, Elisa Sacco, Johan Vergauwen, Georges G. E. Gielen
2017	B	`conf`	Automatic testing of analog ICs for latent defects using topology modification. ETS Nektar Xama, Anthony Coyette, Baris Esen, Wim Dobbelaere, Ronny Vanhooren, Georges G. E. Gielen
2017	—	`conf`	Drift mitigation in integrated sensor interfaces. IWASI Georges G. E. Gielen, Jorge Marin, Elisa Sacco
2017	A	`conf`	Non-intrusive detection of defects in mixed-signal integrated circuits using light activation. ITC Baris Esen, Anthony Coyette, Nektar Xama, Wim Dobbelaere, Ronny Vanhooren, Georges G. E. Gielen
2016	—	`conf`	28.5 A 0.6V 0.015mm2 time-based biomedical readout for ambulatory applications in 40nm CMOS. ISSCC Rachit Mohan, Samira Zaliasl, Georges G. E. Gielen, Chris Van Hoof, Nick Van Helleputte, Refet Firat Yazicioglu
2016	—	`conf`	A column-and-row-parallel CMOS image sensor with thermal and 1/f noise suppression techniques. ESSCIRC Ha Le-Thai, Adi Xhakoni, Georges G. E. Gielen
2016	B	`conf`	A surrogate model assisted evolutionary algorithm for computationally expensive design optimization problems with discrete variables. CEC Bo Liu, Nan Sun, Qingfu Zhang, Vic Grout, Georges G. E. Gielen
2016	A	`conf`	Analog fault coverage improvement using final-test dynamic part average testing. ITC Wim Dobbelaere, Ronny Vanhooren, Willy De Man, Koen Matthijs, Anthony Coyette, Baris Esen, Georges G. E. Gielen
2016	J	`jnl`	Automatic generation of test infrastructures for analog integrated circuits by controllability and observability co-optimization. Integr. Anthony Coyette, Baris Esen, Wim Dobbelaere, Ronny Vanhooren, Georges G. E. Gielen
2016	A	`conf`	Automatic test signal generation for mixed-signal integrated circuits using circuit partitioning and interval analysis. ITC Anthony Coyette, Baris Esen, Wim Dobbelaere, Ronny Vanhooren, Georges G. E. Gielen
2016	A	`conf`	Effective DC fault models and testing approach for open defects in analog circuits. ITC Baris Esen, Anthony Coyette, Georges G. E. Gielen, Wim Dobbelaere, Ronny Vanhooren
2016	J	`jnl`	Time-Based Sensor Interface Circuits in CMOS and Carbon Nanotube Technologies. IEEE Trans. Circuits Syst. I Regul. Pap. Georges G. E. Gielen, Jelle Van Rethy, Jorge Marin, Max M. Shulaker, Gage Hills, H.-S. Philip Wong, Subhasish Mitra
2015	J	`jnl`	A 40-MHz Bandwidth 0-2 MASH VCO-Based Delta-Sigma ADC With 35-fJ/Step FoM. IEEE Trans. Circuits Syst. II Express Briefs Peng Zhu, Xinpeng Xing, Georges G. E. Gielen
2015	J	`jnl`	A 42 fJ/Step-FoM Two-Step VCO-Based Delta-Sigma ADC in 40 nm CMOS. IEEE J. Solid State Circuits Xinpeng Xing, Georges G. E. Gielen
2015	—	`conf`	A lowpass/bandpass reconfigurable continuous-time ΔΣ ADC for software-defined radio. ASICON Xinpeng Xing, Gaozhan Cai, Georges G. E. Gielen
2015	C	`conf`	A presence-based control strategy solution for HVAC systems. ICCE Iman Khajenasiri, Joseph Virgone, Georges G. E. Gielen
2015	Misc	`conf`	Automated testing of mixed-signal integrated circuits by topology modification. VTS Anthony Coyette, Baris Esen, Ronny Vanhooren, Wim Dobbelaere, Georges G. E. Gielen
2015	B	`conf`	Automatic generation of autonomous built-in observability structures for analog circuits. ETS Anthony Coyette, Baris Esen, Ronny Vanhooren, Wim Dobbelaere, Georges G. E. Gielen
2015	—	`conf`	Design of low-power sensor interfaces in the IoT era. IWASI Georges G. E. Gielen
2015	J	`jnl`	Development of an Ultralow-Power Injection-Locked PSK Receiver Architecture. IEEE Trans. Circuits Syst. II Express Briefs Valentijn De Smedt, Georges G. E. Gielen, Wim Dehaene
2015	C	`conf`	Time-based sensor interface circuits in carbon nanotube technology. ISCAS Georges G. E. Gielen, Jelle Van Rethy, Max M. Shulaker, Gage Hills, H.-S. Philip Wong, Subhasish Mitra
2014	—	`conf`	"All Programmable SOC FPGA for networking and computing in big data infrastructure". ASP-DAC Ivo Bolsens, Georges G. E. Gielen, Kaushik Roy, Ulf Schneider
2014	J	`jnl`	A 132-dB Dynamic-Range Global-Shutter Stacked Architecture for High-Performance Imagers. IEEE Trans. Circuits Syst. II Express Briefs Adi Xhakoni, Georges G. E. Gielen
2014	—	`conf`	A 40MHz-BW 35fJ/step-FoM nonlinearity-cancelling two-step ADC with dual-input VCO-based quantizer. ESSCIRC Peng Zhu, Xinpeng Xing, Georges G. E. Gielen
2014	J	`jnl`	A Gaussian Process Surrogate Model Assisted Evolutionary Algorithm for Medium Scale Expensive Optimization Problems. IEEE Trans. Evol. Comput. Bo Liu, Qingfu Zhang, Georges G. E. Gielen
2014	J	`jnl`	An Implantable 455-Active-Electrode 52-Channel CMOS Neural Probe. IEEE J. Solid State Circuits Carolina Mora Lopez, Alexandru Andrei, Srinjoy Mitra, Marleen Welkenhuysen, Wolfgang Eberle, Carmen Bartic, Robert Puers, Refet Firat Yazicioglu, Georges G. E. Gielen
2014	—	`book`	Automated Design of Analog and High-frequency Circuits - A Computational Intelligence Approach Bo Liu, Georges G. E. Gielen, Francisco V. Fernández
2014	—	`conf`	Automatic generation of electro-thermal models with TRAPPIST. ICECS Dimitri de Jonghe, Georges G. E. Gielen, Renaud Gillon
2014	B	`conf`	Behavioral study of the surrogate model-aware evolutionary search framework. IEEE Congress on Evolutionary Computation Bo Liu, Qin Chen, Qingfu Zhang, Georges G. E. Gielen, Vic Grout
2014	—	`conf`	Design and implementation of a multi-standard event-driven energy management system for smart buildings. GCCE Iman Khajenasiri, Edoardo Patti, Marco Jahn, Andrea Acquaviva, Marian Verhelst, Enrico Macii, Georges G. E. Gielen
2014	A	`conf`	Design and test of analog circuits towards sub-ppm level. ITC Georges G. E. Gielen, Wim Dobbelaere, Ronny Vanhooren, Anthony Coyette, Baris Esen
2014	C	`conf`	Design of a frequency reference based on a PVT-independent transmission line delay. ISCAS Florian De Roose, Valentijn De Smedt, Wouter Volkaerts, Michiel Steyaert, Georges G. E. Gielen, Patrick Reynaert, Wim Dehaene
2014	J	`jnl`	GASPAD: A General and Efficient mm-Wave Integrated Circuit Synthesis Method Based on Surrogate Model Assisted Evolutionary Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bo Liu, Dixian Zhao, Patrick Reynaert, Georges G. E. Gielen
2014	B	`conf`	Network on Chip optimization based on surrogate model assisted evolutionary algorithms. IEEE Congress on Evolutionary Computation Mengyuan Wu, Ammar Karkar, Bo Liu, Alex Yakovlev, Georges G. E. Gielen, Vic Grout
2014	B	`conf`	Optimization of analog fault coverage by exploiting defect-specific masking. ETS Anthony Coyette, Georges G. E. Gielen, Ronny Vanhooren, Wim Dobbelaere
2014	J	`jnl`	Scalable Bang-Bang Phase-Locked-Loop-based integrated sensor interfaces. Microelectron. J. Jelle Van Rethy, Hans Danneels, Georges G. E. Gielen
2014	J	`jnl`	Sensor-to-Digital Interface Built Entirely With Carbon Nanotube FETs. IEEE J. Solid State Circuits Max M. Shulaker, Jelle Van Rethy, Gage Hills, Hai Wei, Hong-Yu Chen, Georges G. E. Gielen, H.-S. Philip Wong, Subhasish Mitra
2014	J	`jnl`	Sparse ε-tube support vector regression by active learning. Soft Comput. Vladimir Ceperic, Georges G. E. Gielen, Adrijan Baric
2014	J	`jnl`	Transient Behavior and Phase Noise Performance of Pulsed-Harmonic Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. Valentijn De Smedt, Georges G. E. Gielen, Wim Dehaene
2013	—	`conf`	A 40MHz-BW two-step open-loop VCO-based ADC with 42fJ/step FoM in 40nm CMOS. ESSCIRC Xinpeng Xing, Peng Gao, Georges G. E. Gielen
2013	—	`conf`	A 40nm-CMOS, 72 µW injection-locked timing reference and 1.8 Mbit/s coordination receiver for wireless sensor networks. ESSCIRC Valentijn De Smedt, Georges G. E. Gielen, Wim Dehaene
2013	A	`conf`	A low-power and low-voltage BBPLL-based sensor interface in 130nm CMOS for wireless sensor networks. DATE Jelle Van Rethy, Hans Danneels, Valentijn De Smedt, Wim Dehaene, Georges G. E. Gielen
2013	J	`jnl`	An Efficient Evolutionary Algorithm for Chance-Constrained Bi-Objective Stochastic Optimization. IEEE Trans. Evol. Comput. Bo Liu, Qingfu Zhang, Francisco V. Fernández, Georges G. E. Gielen
2013	—	`conf`	An implantable 455-active-electrode 52-channel CMOS neural probe. ISSCC Carolina Mora Lopez, Alexandru Andrei, Srinjoy Mitra, Marleen Welkenhuysen, Wolfgang Eberle, Carmen Bartic, Robert Puers, Refet Firat Yazicioglu, Georges G. E. Gielen
2013	—	`conf`	Black-Box Modelling of AC-DC Rectifiers for RFID Applications Using Support Vector Regression Machines. UKSim Vladimir Ceperic, Georges G. E. Gielen, Adrijan Baric
2013	J	`jnl`	Calibration of DAC Mismatch Errors in ΣΔ ADCs Based on a Sine-Wave Measurement. IEEE Trans. Circuits Syst. II Express Briefs Maarten De Bock, Xinpeng Xing, Ludo Weyten, Georges G. E. Gielen, Pieter Rombouts
2013	—	`conf`	Developing engineering-oriented educational workshops within a student branch. EUROCON Jan Verveckken, Frederik Geth, Borbála Hunyadi, Jef Beerten, Niels Leemput, Juan Van Roy, Pieter Tielens, Valentijn De Smedt, Sandro Iacovella, Ninah Koolen, Hans De Clercq, Johan Driesen, Georges G. E. Gielen, Robert Puers, Joos Vandewalle, Sabine Van Huffel, Ronnie Belmans, Geert Deconinck, Wim Dehaene
2013	—	`conf`	Experimental demonstration of a fully digital capacitive sensor interface built entirely using carbon-nanotube FETs. ISSCC Max M. Shulaker, Jelle Van Rethy, Gage Hills, Hong-Yu Chen, Georges G. E. Gielen, H.-S. Philip Wong, Subhasish Mitra
2013	A	`conf`	Extracting analytical nonlinear models from analog circuits by recursive vector fitting of transfer function trajectories. DATE Dimitri de Jonghe, Dirk Deschrijver, Tom Dhaene, Georges G. E. Gielen
2013	—	`conf`	Impact of transistor aging on RF low noise amplifier performance of 28nm technology: Reliability assessment. ICECS Swaraj Mahato, Georges G. E. Gielen
2013	J	`jnl`	Miniaturization of UWB Antennas and its Influence on Antenna-Transceiver Performance in Impulse-UWB Communication. Wirel. Pers. Commun. Soheil Radiom, Majid Baghaei Nejad, Hadi Aliakbarian, Li-Rong Zheng, Guy A. E. Vandenbosch, Georges G. E. Gielen
2013	J	`jnl`	Mixed-signal template-based reduction scheme for stimulus artifact removal in electrical stimulation. Medical Biol. Eng. Comput. Thi Kim Thoa Nguyen, Silke Musa, Wolfgang Eberle, Carmen Bartic, Georges G. E. Gielen
2013	J	`jnl`	Performance Analysis of Energy-Efficient BBPLL-Based Sensor-to-Digital Converters. IEEE Trans. Circuits Syst. I Regul. Pap. Jelle Van Rethy, Hans Danneels, Georges G. E. Gielen
2013	A*	`conf`	Sacha: the Stanford carbon nanotube controlled handshaking robot. DAC Max M. Shulaker, Jelle Van Rethy, Gage Hills, Hong-Yu Chen, Georges G. E. Gielen, H.-S. Philip Wong, Subhasish Mitra
2013	A	`conf`	Stochastic degradation modeling and simulation for analog integrated circuits in nanometer CMOS. DATE Georges G. E. Gielen, Elie Maricau
2013	J	`jnl`	Supply-Noise-Resilient Design of a BBPLL-Based Force-Balanced Wheatstone Bridge Interface in 130-nm CMOS. IEEE J. Solid State Circuits Jelle Van Rethy, Hans Danneels, Valentijn De Smedt, Wim Dehaene, Georges G. E. Gielen
2013	—	`conf`	Timing-based integrated sensor interfaces: Hype or promise? IWASI Georges G. E. Gielen
2012	—	`conf`	A 127 μW exact timing reference for Wireless Sensor Networks based on injection locking. ESSCIRC Valentijn De Smedt, Georges G. E. Gielen, Wim Dehaene
2012	J	`jnl`	A Multichannel Integrated Circuit for Electrical Recording of Neural Activity, With Independent Channel Programmability. IEEE Trans. Biomed. Circuits Syst. Carolina Mora Lopez, Dimiter Prodanov, Dries Braeken, Ivan Gligorijevic, Wolfgang Eberle, Carmen Bartic, Robert Puers, Georges G. E. Gielen
2012	A	`conf`	A fast analog circuit yield estimation method for medium and high dimensional problems. DATE Bo Liu, Jarir Messaoudi, Georges G. E. Gielen
2012	A	`conf`	Advances in variation-aware modeling, verification, and testing of analog ICs. DATE Dimitri de Jonghe, Elie Maricau, Georges G. E. Gielen, Trent McConaghy, Bratislav Tasic, Haralampos-G. D. Stratigopoulos
2012	J	`jnl`	An Efficient High-Frequency Linear RF Amplifier Synthesis Method Based on Evolutionary Computation and Machine Learning Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bo Liu, Noël Deferm, Dixian Zhao, Patrick Reynaert, Georges G. E. Gielen
2012	J	`jnl`	Characterization of Analog Circuits Using Transfer Function Trajectories. IEEE Trans. Circuits Syst. I Regul. Pap. Dimitri de Jonghe, Georges G. E. Gielen
2012	J	`jnl`	Degradation-Resilient Design of a Self-Healing xDSL Line Driver in 90 nm CMOS. IEEE J. Solid State Circuits Pieter De Wit, Georges G. E. Gielen
2012	A	`conf`	Design of an intrinsically-linear double-VCO-based ADC with 2 DATE Peng Gao, Xinpeng Xing, Jan Craninckx, Georges G. E. Gielen
2012	—	`conf`	Designing reliable analog circuits in an unreliable world. CICC Georges G. E. Gielen, Elie Maricau, Pieter De Wit
2012	A*	`conf`	Efficient multi-objective synthesis for microwave components based on computational intelligence techniques. DAC Bo Liu, Hadi Aliakbarian, Soheil Radiom, Guy A. E. Vandenbosch, Georges G. E. Gielen
2012	A	`conf`	Hierarchical analog circuit reliability analysis using multivariate nonlinear regression and active learning sample selection. DATE Elie Maricau, Dimitri de Jonghe, Georges G. E. Gielen
2012	A	`conf`	Impact of TSV area on the dynamic range and frame rate performance of 3D-integrated image sensors. DATE Adi Xhakoni, David San Segundo Bello, Georges G. E. Gielen
2012	—	`conf`	Offset measurement method for accurate characterization of BTI-induced degradation in opamps. ICECS Swaraj Mahato, Pieter De Wit, Elie Maricau, Georges G. E. Gielen
2012	J	`jnl`	Recurrent sparse support vector regression machines trained by active learning in the time-domain. Expert Syst. Appl. Vladimir Ceperic, Georges G. E. Gielen, Adrijan Baric
2012	B	`conf`	Self-adaptive lower confidence bound: A new general and effective prescreening method for Gaussian Process surrogate model assisted evolutionary algorithms. IEEE Congress on Evolutionary Computation Bo Liu, Qingfu Zhang, Francisco V. Fernández, Georges G. E. Gielen
2012	J	`jnl`	Sparse multikernel support vector regression machines trained by active learning. Expert Syst. Appl. Vladimir Ceperic, Georges G. E. Gielen, Adrijan Baric
2012	—	`conf`	Towards a noise prediction model for in vivo neural recording. EMBC Carolina Mora Lopez, Marleen Welkenhuysen, Silke Musa, Wolfgang Eberle, Carmen Bartic, Robert Puers, Georges G. E. Gielen
2011	—	`conf`	A 0.6V to 1.6V, 46μW voltage and temperature independent 48 MHz pulsed LC oscillator for RFID tags. A-SSCC Valentijn De Smedt, Georges G. E. Gielen, Wim Dehaene
2011	C	`conf`	A 16-channel low-noise programmable system for the recording of neural signals. ISCAS Carolina Mora Lopez, Dries Braeken, Carmen Bartic, Robert Puers, Georges G. E. Gielen, Wolfgang Eberle
2011	—	`conf`	A 40MHz 12bit 84.2dB-SFDR continuous-time delta-sigma modulator in 90nm CMOS. A-SSCC Xinpeng Xing, Maarten De Bock, Pieter Rombouts, Georges G. E. Gielen
2011	J	`jnl`	A Rigorous Approach to the Robust Design of Continuous-Time Sigma-Delta Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. Bart De Vuyst, Pieter Rombouts, Georges G. E. Gielen
2011	J	`jnl`	A Volterra Series Nonlinear Model of the Sampling Distortion in Flash ADCs Due to Substrate Noise Coupling. IEEE Trans. Circuits Syst. II Express Briefs Athanasios Stefanou, Georges G. E. Gielen
2011	—	`conf`	A failure-resilient xDSL line driver with on-chip degradation monitor. ESSCIRC Pieter De Wit, Georges G. E. Gielen
2011	—	`conf`	A fully-digital, 0.3V, 270 nW capacitive sensor interface without external references. ESSCIRC Hans Danneels, Kristof Coddens, Georges G. E. Gielen
2011	C	`conf`	A novel operating-point driven method for the sizing of analog IC. ISCAS Bo Liu, Murat Pak, Xuezhi Zheng, Georges G. E. Gielen
2011	A	`conf`	Analog circuit reliability in sub-32 nanometer CMOS: Analysis and mitigation. DATE Georges G. E. Gielen, Elie Maricau, Pieter De Wit
2011	C	`conf`	Circuits and systems engineering education through interdisciplinary team-based design projects. ISCAS Wim Dehaene, Georges G. E. Gielen, Geert Deconinck, Johan Driesen, Marc Moonen, Bart Nauwelaers, Chris Van Hoof, Patrick Wambacq
2011	J	`jnl`	Computer-Aided Analog Circuit Design for Reliability in Nanometer CMOS. IEEE J. Emerg. Sel. Topics Circuits Syst. Elie Maricau, Georges G. E. Gielen
2011	A	`conf`	Efficient analytical macromodeling of large analog circuits by Transfer Function Trajectories. ICCAD Dimitri de Jonghe, Georges G. E. Gielen
2011	J	`jnl`	Efficient and Accurate Statistical Analog Yield Optimization and Variation-Aware Circuit Sizing Based on Computational Intelligence Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bo Liu, Francisco V. Fernández, Georges G. E. Gielen
2011	A	`conf`	Global optimization of integrated transformers for high frequency microwave circuits using a Gaussian process based surrogate model. DATE Bo Liu, Ying He, Patrick Reynaert, Georges G. E. Gielen
2011	—	`conf`	Impact analysis of stochastic transistor aging on current-steering DACs in 32nm CMOS. ICECS Simon Vanden Bussche, Pieter De Wit, Elie Maricau, Georges G. E. Gielen
2011	A	`conf`	Stochastic circuit reliability analysis. DATE Elie Maricau, Georges G. E. Gielen
2011	J	`jnl`	Synthesis of Integrated Passive Components for High-Frequency RF ICs Based on Evolutionary Computation and Machine Learning Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bo Liu, Dixian Zhao, Patrick Reynaert, Georges G. E. Gielen
2011	A	`conf`	Systematic design of a programmable low-noise CMOS neural interface for cell activity recording. DATE Carolina Mora Lopez, Silke Musa, Carmen Bartic, Robert Puers, Georges G. E. Gielen, Wolfgang Eberle
2011	—	`conf`	Transistor aging-induced degradation of analog circuits: Impact analysis and design guidelines. ESSCIRC Elie Maricau, Georges G. E. Gielen
2011	J	`jnl`	Trustworthy Genetic Programming-Based Synthesis of Analog Circuit Topologies Using Hierarchical Domain-Specific Building Blocks. IEEE Trans. Evol. Comput. Trent McConaghy, Pieter Palmers, Michiel Steyaert, Georges G. E. Gielen
2010	C	`conf`	A 0.5 V-1.4 V supply-independent frequency-based analog-to-digital converter with fast start-up time for wireless sensor networks. ISCAS Wouter Volkaerts, Bart Marien, Hans Danneels, Valentijn De Smedt, Patrick Reynaert, Wim Dehaene, Georges G. E. Gielen
2010	J	`jnl`	A Reconfigurable, 130 nm CMOS 108 pJ/pulse, Fully Integrated IR-UWB Receiver for Communication and Precise Ranging. IEEE J. Solid State Circuits Nick Van Helleputte, Marian Verhelst, Wim Dehaene, Georges G. E. Gielen
2010	A	`conf`	An accurate and efficient yield optimization method for analog circuits based on computing budget allocation and memetic search technique. DATE Bo Liu, Francisco V. Fernández, Georges G. E. Gielen
2010	B	`conf`	An enhanced MOEA/D-DE and its application to multiobjective analog cell sizing. IEEE Congress on Evolutionary Computation Bo Liu, Francisco V. Fernández, Qingfu Zhang, Murat Pak, Suha Sipahi, Georges G. E. Gielen
2010	A	`conf`	Design automation towards reliable analog integrated circuits. ICCAD Georges G. E. Gielen, Elie Maricau, Pieter De Wit
2010	J	`jnl`	Efficient Variability-Aware NBTI and Hot Carrier Circuit Reliability Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Elie Maricau, Georges G. E. Gielen
2010	C	`conf`	Efficient simulation model for DAC dynamic properties. ISCAS Pieter De Wit, Georges G. E. Gielen
2010	J	`jnl`	Energy Normalized Correlation for Signal Acquisition in Power-Control-Absent UWB Networks. IEEE Commun. Lett. Zheng Li, Georges G. E. Gielen
2010	J	`jnl`	Far-Field On-Chip Antennas Monolithically Integrated in a Wireless-Powered 5.8-GHz Downlink/UWB Uplink RFID Tag in 0.18-μm Standard CMOS. IEEE J. Solid State Circuits Soheil Radiom, Majid Baghaei Nejad, Karim Aghdam, Guy A. E. Vandenbosch, Li-Rong Zheng, Georges G. E. Gielen
2010	J	`jnl`	The Nyquist Criterion: A Useful Tool for the Robust Design of Continuous-Time SigmaDelta Modulators. IEEE Trans. Circuits Syst. II Express Briefs Bart De Vuyst, Pieter Rombouts, Jeroen De Maeyer, Georges G. E. Gielen
2010	A	`conf`	Variability-aware reliability simulation of mixed-signal ICs with quasi-linear complexity. DATE Elie Maricau, Georges G. E. Gielen
2009	—	`conf`	A 0.4-1.4V 24MHz fully integrated 33µW, 104ppm/V supply-independent oscillator for RFIDs. ESSCIRC Valentijn De Smedt, Wim Dehaene, Georges G. E. Gielen
2009	J	`jnl`	A 3-tier UWB-based indoor localization system for ultra-low-power sensor networks. IEEE Trans. Wirel. Commun. Zheng Li, Wim Dehaene, Georges G. E. Gielen
2009	J	`jnl`	A 70 pJ/Pulse Analog Front-End in 130 nm CMOS for UWB Impulse Radio Receivers. IEEE J. Solid State Circuits Nick Van Helleputte, Georges G. E. Gielen
2009	A	`conf`	A design methodology for fully reconfigurable Delta-Sigma data converters. DATE Yi Ke, Jan Craninckx, Georges G. E. Gielen
2009	—	`conf`	A fuzzy selection based constraint handling method for multi-objective optimization of analog cells. ECCTD Bo Liu, Francisco V. Fernández, Peng Gao, Georges G. E. Gielen
2009	J	`jnl`	A memetic approach to the automatic design of high-performance analog integrated circuits. ACM Trans. Design Autom. Electr. Syst. Bo Liu, Francisco V. Fernández, Georges G. E. Gielen, Rafael Castro-López, Elisenda Roca
2009	C	`conf`	A methodology for measuring transistor ageing effects towards accurate reliability simulation. IOLTS Elie Maricau, Georges G. E. Gielen
2009	—	`conf`	A reconfigurable, 0.13µm CMOS 110pJ/pulse, fully integrated IR-UWB receiver for communication and sub-cm ranging. ISSCC Marian Verhelst, Nick Van Helleputte, Georges G. E. Gielen, Wim Dehaene
2009	—	`conf`	A remote-powered RFID tag with 10Mb/s UWB uplink and -18.5dBm sensitivity UHF downlink in 0.18µm CMOS. ISSCC Majid Baghaei Nejad, David S. Mendoza, Zhuo Zou, Soheil Radiom, Georges G. E. Gielen, Li-Rong Zheng, Hannu Tenhunen
2009	J	`jnl`	ANTIGONE: Top-down creation of analog-to-digital converter architectures. Integr. Ewout Martens, Georges G. E. Gielen
2009	C	`conf`	Design tools and circuit solutions for degradation-resilient analog circuits in nanometer CMOS. DDECS Georges G. E. Gielen
2009	A	`conf`	Efficient reliability simulation of analog ICs including variability and time-varying stress. DATE Elie Maricau, Georges G. E. Gielen
2009	B	`conf`	Fuzzy selection based differential evolution algorithm for analog cell sizing capturing imprecise human intentions. IEEE Congress on Evolutionary Computation Bo Liu, Francisco V. Fernández, Georges G. E. Gielen
2009	J	`jnl`	Globally Reliable Variation-Aware Sizing of Analog Integrated Circuits via Response Surfaces and Structural Homotopy. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Trent McConaghy, Georges G. E. Gielen
2009	A*	`conf`	Guess, solder, measure, repeat: how do I get my mixed-signal chip right? DAC Geoffrey Ying, Andreas Kuehlmann, Kenneth S. Kundert, Georges G. E. Gielen, Eric Grimme, Martin O'Leary, Sandeep Tare, Warren Wong
2009	A	`conf`	Health-care electronics The market, the challenges, the progress. DATE Wolfgang Eberle, Ashwin S. Mecheri, Thi Kim Thoa Nguyen, Georges G. E. Gielen, Raymond Campagnolo, Alison J. Burdett, Chris Toumazou, Bart Volckaerts
2009	—	`conf`	Less expensive and high quality stopping criteria for MC-based analog IC yield optimization. ICECS Bo Liu, Francisco V. Fernández, Dimitri de Jonghe, Georges G. E. Gielen
2009	A	`conf`	Massively multi-topology sizing of analog integrated circuits. DATE Pieter Palmers, Trent McConaghy, Michiel Steyaert, Georges G. E. Gielen
2009	—	`conf`	Mitigation of the sampling and substrate noise induced distortion in regenerative comparators by adaptive interpolation. ECCTD Athanasios Stefanou, Georges G. E. Gielen
2009	—	`conf`	Optimizing current conveyors by evolutionary algorithms including differential evolution. ICECS Ivick Guerra-Gómez, Esteban Tlelo-Cuautle, Trent McConaghy, Georges G. E. Gielen
2009	C	`conf`	Prediction of Non-uniform Sampling Distortion Due to Substrate Noise Coupling in Regenerative Comparators. ISCAS Athanasios Stefanou, Georges G. E. Gielen
2009	—	`conf`	RFID, where are they? ESSCIRC Wim Dehaene, Georges G. E. Gielen, Michiel Steyaert, Hans Danneels, V. Desmedt, Christophe De Roover, Z. Li, Marian Verhelst, Nick Van Helleputte, S. Radioma, C. Walravensa, L. Pleysier
2009	J	`jnl`	Template-Free Symbolic Performance Modeling of Analog Circuits via Canonical-Form Functions and Genetic Programming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Trent McConaghy, Georges G. E. Gielen
2009	—	`conf`	Towards automated extraction of EMC-aware trajectory-based macromodels for analog circuits. ECCTD Georges G. E. Gielen, Dimitri de Jonghe, Johan Loeckx
2009	—	`conf`	Ultra low power flash ADC for UWB transceiver applications. ECCTD Mohammad Masoumi, Erik Markert, Ulrich Heinkel, Georges G. E. Gielen
2009	J	`jnl`	Variation-Aware Structural Synthesis of Analog Circuits via Hierarchical Building Blocks and Structural Homotopy. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Trent McConaghy, Pieter Palmers, Michiel Steyaert, Georges G. E. Gielen
2008	—	`conf`	A 46pJ/pulse analog front-end in 130nm CMOS for UWB impulse radio receivers. ESSCIRC Nick Van Helleputte, Georges G. E. Gielen
2008	J	`jnl`	A Design Approach for Power-Optimized Fully Reconfigurable Delta Sigma A/D Converter for 4G Radios. IEEE Trans. Circuits Syst. II Express Briefs Yi Ke, Jan Craninckx, Georges G. E. Gielen
2008	C	`conf`	A low-power mixing DAC IR-UWB-receiver. ISCAS Hans Danneels, Marian Verhelst, Pieter Palmers, Wim Vereecken, Bruno Boury, Wim Dehaene, Michiel Steyaert, Georges G. E. Gielen
2008	J	`jnl`	An analytical model for hot carrier degradation in nanoscale CMOS suitable for the simulation of degradation in analog IC applications. Microelectron. Reliab. Elie Maricau, Pieter De Wit, Georges G. E. Gielen
2008	J	`jnl`	Analysis of quantization effects on high-order function neural networks. Appl. Intell. Minghu Jiang, Georges G. E. Gielen
2008	A	`conf`	Automated extraction of expert knowledge in analog topology selection and sizing. ICCAD Trent McConaghy, Pieter Palmers, Georges G. E. Gielen, Michiel Steyaert
2008	J	`jnl`	Classification of analog synthesis tools based on their architecture selection mechanisms. Integr. Ewout Martens, Georges G. E. Gielen
2008	A	`conf`	Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies. DATE Georges G. E. Gielen, Pieter De Wit, Elie Maricau, Johan Loeckx, Javier Martín-Martínez, Ben Kaczer, Guido Groeseneken, Rosana Rodríguez, Montserrat Nafría
2008	A	`conf`	From Transistor to PLL - Analogue Design and EDA Methods. DATE David M. Binkley, Helmut E. Graeb, Georges G. E. Gielen, Jaijeet S. Roychowdhury
2008	—	`conf`	ISCLEs: Importance Sampled Circuit Learning Ensembles for Trustworthy Analog Circuit Topology Synthesis. ICES Peng Gao, Trent McConaghy, Georges G. E. Gielen
2008	A	`conf`	Importance sampled circuit learning ensembles for robust analog IC design. ICCAD Peng Gao, Trent McConaghy, Georges G. E. Gielen
2007	A	`ed.`	2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007 ICCAD Georges G. E. Gielen
2007	J	`jnl`	A 14-bit 200-MHz Current-Steering DAC With Switching-Sequence Post-Adjustment Calibration. IEEE J. Solid State Circuits Tao Chen, Georges G. E. Gielen
2007	A	`conf`	An efficient methodology for hierarchical synthesis of mixed-signal systems with fully integrated building block topology selection. DATE Tom Eeckelaert, Raf Schoofs, Georges G. E. Gielen, Michiel Steyaert, Willy M. C. Sansen
2007	J	`jnl`	Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? CoRR Georges G. E. Gielen, Wim Dehaene, Phillip Christie, Dieter Draxelmayr, Edmond Janssens, Karen Maex, Ted Vucurevich
2007	—	`conf`	Analyzing the performance degradation of flash A/D converters due to substrate noise coupling. ECCTD Athanasios Stefanou, Georges G. E. Gielen
2007	—	`conf`	Automated synthesis of complex analog circuits. ECCTD Georges G. E. Gielen, Tom Eeckelaert, Ewout Martens, Trent McConaghy
2007	J	`jnl`	CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming CoRR Trent McConaghy, Tom Eeckelaert, Georges G. E. Gielen
2007	—	`conf`	Design tool solutions for mixed-signal/RF circuit design in CMOS nanometer technologies. ASP-DAC Georges G. E. Gielen
2007	—	`conf`	Effect of Mismatch on Substrate Noise Coupling on Flash A/D Converters. ICECS Athanasios Stefanou, Georges G. E. Gielen
2007	—	`conf`	Future trends for wireless communication frontends in nanometer CMOS. ACM Great Lakes Symposium on VLSI Georges G. E. Gielen
2007	J	`jnl`	Guest Editorial [intro. to the special issue on the 2006 IEEE/ACM Design, Automation and Test in Europe Conference]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Georges G. E. Gielen, Donatella Sciuto
2007	J	`jnl`	Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs. Proc. IEEE Rob A. Rutenbar, Georges G. E. Gielen, Jaijeet S. Roychowdhury
2007	—	`conf`	Optimal Design Methodology for High-Order Continuous-Time Wideband Delta-Sigma Converters. ICECS Yi Ke, Soheil Radiom, Hamidreza Rezaee, Guy A. E. Vandenbosch, Jan Craninckx, Georges G. E. Gielen
2007	C	`conf`	Scalable Gate-Level Models for Power and Timing Analysis. ISCAS Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2007	A*	`conf`	Simultaneous Multi-Topology Multi-Objective Sizing Across Thousands of Analog Circuit Topologies. DAC Trent McConaghy, Pieter Palmers, Georges G. E. Gielen, Michiel Steyaert
2007	J	`jnl`	The Analysis and Improvement of a Current-Steering DAC's Dynamic SFDR - II: The Output-Dependent Delay Differences. IEEE Trans. Circuits Syst. I Regul. Pap. Tao Chen, Georges G. E. Gielen
2006	—	`conf`	A Continuous-Time Delta-Sigma Modulator for 802.11a/b/g WLAN Implemented with a Hierarchical Bottom-up Optimization Methodology. ICECS Raf Schoofs, Tom Eeckelaert, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen
2006	C	`conf`	A behavioral model of sampled-data systems in the phase-frequency transfer domain for architectural exploration of transceivers. ISCAS Ewout Martens, Georges G. E. Gielen
2006	J	`jnl`	Analyzing continuous-time Delta-Sigma-Modulators with generic behavioral models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ewout Martens, Georges G. E. Gielen
2006	C	`conf`	Assessment of parameter extraction methods for integrated inductor design and model validation. ISCAS Alkis A. Hatzopoulos, Stefanos Stefanou, Georges G. E. Gielen, Dominique Schreurs
2006	A	`conf`	Automation in mixed-signal design: challenges and solutions in the wake of the nano era. ICCAD Trent McConaghy, Georges G. E. Gielen
2006	A	`conf`	Canonical form functions as a simple means for genetic programming to evolve human-interpretable functions. GECCO Trent McConaghy, Georges G. E. Gielen
2006	J	`jnl`	Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2006	A	`conf`	Double-strength CAFFEINE: fast template-free symbolic modeling of analog circuits via implicit canonical form functions and explicit introns. DATE Trent McConaghy, Georges G. E. Gielen
2006	J	`jnl`	Evolution of substrate noise generation mechanisms with CMOS technology scaling. IEEE Trans. Circuits Syst. I Regul. Pap. Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man
2006	C	`conf`	Generic Behavioral Modeling of Analog and Mixed-Signal Systems. FDL Ewout Martens, Georges G. E. Gielen
2006	A*	`conf`	Hierarchical bottom--up analog optimization methodology validated by a delta-sigma A/D converter design for the 802.11a/b/g standard. DAC Tom Eeckelaert, Raf Schoofs, Georges G. E. Gielen, Michiel Steyaert, Willy M. C. Sansen
2006	A	`ed.`	Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006 DATE Georges G. E. Gielen
2006	—	`ed.`	Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, DATE 2006, Munich, Germany, March 6-10, 2006 DATE Designers' Forum Georges G. E. Gielen
2006	J	`jnl`	SWAN: high-level simulation methodology for digital substrate noise generation. IEEE Trans. Very Large Scale Integr. Syst. Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2006	J	`jnl`	The analysis and improvement of a current-steering DACs dynamic SFDR-I: the cell-dependent delay differences. IEEE Trans. Circuits Syst. I Regul. Pap. Tao Chen, Georges G. E. Gielen
2006	A	`conf`	Top-down heterogeneous synthesis of analog and mixed-signal systems. DATE Ewout Martens, Georges G. E. Gielen
2005	—	`conf`	A CAD Platform for Sensor Interfaces in Low-Power Applications. PATMOS Didier Van Reeth, Georges G. E. Gielen
2005	—	`conf`	A design automation tool for low-power signal filters for use in sensor interfaces. ECCTD Didier Van Reeth, Georges G. E. Gielen
2005	J	`jnl`	An Efficient, Fully Parasitic-Aware Power Amplifier Design Optimization Tool. IEEE Trans. Circuits Syst. I Regul. Pap. João Ramos, Kenneth Francken, Georges G. E. Gielen, Michiel Steyaert
2005	A	`conf`	Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? DATE Georges G. E. Gielen, Wim Dehaene, Phillip Christie, Dieter Draxelmayr, Edmond Janssens, Karen Maex, Ted Vucurevich
2005	—	`conf`	Analysis of coil parameter extraction methods for on-chip inductor design. ECCTD Alkis A. Hatzopoulos, Stefanos Stefanou, Georges G. E. Gielen, Dominique Schreurs
2005	—	`conf`	Analysis of simulation-driven numerical performance modeling techniques for application to analog circuit optimization. ISCAS (2) Trent McConaghy, Georges G. E. Gielen
2005	—	`conf`	Behavioral modeling and simulation of weakly nonlinear sampled-data systems. ISCAS (3) Ewout Martens, Georges G. E. Gielen
2005	A	`conf`	CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming. DATE Trent McConaghy, Tom Eeckelaert, Georges G. E. Gielen
2005	—	`conf`	CAFFEINE: template-free symbolic model generation of analog circuits via canonical form functions and genetic programming. ESSCIRC Trent McConaghy, Tom Eeckelaert, Georges G. E. Gielen
2005	J	`jnl`	Digital ground bounce reduction by supply current shaping and clock frequency Modulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2005	A	`conf`	Efficient Multiobjective Synthesis of Analog Circuits using Hierarchical Pareto-Optimal Performance Hypersurfaces. DATE Tom Eeckelaert, Trent McConaghy, Georges G. E. Gielen
2005	—	`conf`	Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams. ASP-DAC Huiying Yang, Mukesh Ranjan, Wim Verhaegen, Mengmeng Ding, Ranga Vemuri, Georges G. E. Gielen
2005	—	`conf`	IBMG: interpretable behavioral model generator for nonlinear analog circuits via canonical form functions and genetic programming. ISCAS (5) Trent McConaghy, Georges G. E. Gielen
2005	A*	`conf`	Performance space modeling for hierarchical synthesis of analog integrated circuits. DAC Georges G. E. Gielen, Trent McConaghy, Tom Eeckelaert
2005	—	`conf`	Systematic top-down design of A/D converters. ECCTD Martin Vogels, Georges G. E. Gielen
2005	A	`conf`	Time-Domain Simulation of Sampled Weakly Nonlinear Systems Using Analytical Integration and Orthogonal Polynomial Series. DATE Ewout Martens, Georges G. E. Gielen
2004	—	`conf`	A 14-bit 130-MHz CMOS current-steering DAC with adjustable INL. ESSCIRC Tao Chen, Peter Geens, Geert Van der Plas, Wim Dehaene, Georges G. E. Gielen
2004	—	`conf`	A Bayesian Classifier by Using the Adaptive Construct Algorithm of the RBF Networks. ISNN (1) Minghu Jiang, Dafan Liu, Beixing Deng, Georges G. E. Gielen
2004	A	`conf`	A Phase-Frequency Transfer Description of Analog and Mixed-Signal Front-End Architectures for System-Level Design. DATE Ewout Martens, Georges G. E. Gielen
2004	J	`jnl`	A gradient-error and edge-effect tolerant switching scheme for a high-accuracy DAC. IEEE Trans. Circuits Syst. I Regul. Pap. Jurgen Deveugele, Geert Van der Plas, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen
2004	J	`jnl`	An analytical integration method for the simulation of continuous-time ΔΣ modulators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Georges G. E. Gielen, Kenneth Francken, Ewout Martens, Martin Vogels
2004	—	`conf`	Backpropagation Analysis of the Limited Precision on High-Order Function Neural Networks. ISNN (1) Minghu Jiang, Georges G. E. Gielen
2004	A	`conf`	Digital Ground Bounce Reduction by Phase Modulation of the Clock. DATE Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2004	J	`jnl`	Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. IEEE J. Solid State Circuits Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Lakshmanan Balasubramanian, Kris Tiri, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man
2004	J	`jnl`	Efficient analysis of slow-varying oscillator dynamics. IEEE Trans. Circuits Syst. I Regul. Pap. Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen
2004	A	`conf`	Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models. DATE Mukesh Ranjan, Wim Verhaegen, Anuradha Agarwal, Hemanth Sampath, Ranga Vemuri, Georges G. E. Gielen
2004	—	`conf`	High-level modeling of continuous-time Delta-Sigma A/D-converters using formal models. ASP-DAC Ewout Martens, Georges G. E. Gielen
2004	A*	`conf`	High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects. DAC Geert Van der Plas, Mustafa Badaroglu, Gerd Vandersteen, Petr Dobrovolný, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2004	—	`conf`	Impact of technology scaling on substrate noise generation mechanisms [mixed signal ICs]. CICC Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2004	—	`conf`	Knowledge- and optimization-based design of RF power amplifiers. ISCAS (1) João Ramos, Kenneth Francken, Georges G. E. Gielen, Michiel Steyaert
2004	—	`conf`	Modelling of the impact of the current source output impedance on the SFDR of current-steering CMOS D/A converters. ISCAS (1) Tao Chen, Georges G. E. Gielen
2004	A	`conf`	Performance Modeling of Analog Integrated Circuits Using Least-Squares Support Vector Machines. DATE Tholom Kiely, Georges G. E. Gielen
2004	J	`jnl`	Systematic design exploration of delta-sigma ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. Ovidiu Bajdechi, Georges G. E. Gielen, Johan H. Huijsing
2003	A	`conf`	A Generalized Method for Computing Oscillator Phase Noise Spectra. ICCAD Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen
2003	A	`conf`	A Model of Computation for Continuous-Time ?-? Modulators. DATE Ewout Martens, Georges G. E. Gielen
2003	J	`jnl`	A high-level simulation and synthesis environment for ΔΣ modulators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kenneth Francken, Georges G. E. Gielen
2003	—	`conf`	Analysis of the dynamic SFDR property of high-accuracy current-steering D/A converters. ISCAS (1) Tao Chen, Georges G. E. Gielen
2003	A*	`conf`	Architectural selection of A/D converters. DAC Martin Vogels, Georges G. E. Gielen
2003	A	`conf`	Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver. DATE Wolfgang Eberle, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2003	J	`jnl`	Behavioral modeling of (coupled) harmonic oscillators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen
2003	J	`jnl`	Design techniques and implementation of an 8-bit 200-MS/s interpolating/averaging CMOS A/D converter. IEEE J. Solid State Circuits Koen Uyttenhove, Jan Vandenbussche, Erik Lauwers, Georges G. E. Gielen, Michiel S. J. Steyaert
2003	—	`conf`	Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. ESSCIRC Mustafa Badaroglu, Lakshmanan Balasubramanian, Kris Tiri, Vincent Gravot, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2003	J	`jnl`	Fast Learning Algorithms for Feedforward Neural Networks. Appl. Intell. Minghu Jiang, Georges G. E. Gielen, Bo Zhang, Zhensheng Luo
2003	A	`conf`	Figure of Merit Based Selection of A/D Converters. DATE Martin Vogels, Georges G. E. Gielen
2003	A	`conf`	Generalized Posynomial Performance Modeling. DATE Tom Eeckelaert, Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen
2003	J	`jnl`	Guest editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. H. Alan Mantooth, Georges G. E. Gielen
2003	A	`conf`	HOLMES: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated Circuits. DATE Bart De Smedt, Georges G. E. Gielen
2003	J	`jnl`	Modeling and experimental verification of substrate noise generation in a 220-Kgates WLAN system-on-chip with multiple supplies. IEEE J. Solid State Circuits Mustafa Badaroglu, Stéphane Donnay, Hugo J. De Man, Yann A. Zinzius, Georges G. E. Gielen, Willy Sansen, Tony Fondén, Svante Signell
2003	—	`conf`	Modelling impact of digital substrate noise on embedded regenerative comparators. ESSCIRC Yann A. Zinzius, Georges G. E. Gielen, Willy Sansen
2003	J	`jnl`	PeopleMover: an example of interdisciplinary project-based education in electrical engineering. IEEE Trans. Educ. Walter Daems, Bart De Smedt, Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen, Hugo De Man
2003	J	`jnl`	Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen
2003	J	`jnl`	The Effects of Quantization on Multi-Layer Feedforward Neural Networks. Int. J. Pattern Recognit. Artif. Intell. Minghu Jiang, Georges G. E. Gielen
2003	A	`conf`	Time-Varying, Frequency-Domain Modeling and Analysis of Phase-Locked Loops with Sampling Phase-Frequency Detectors. DATE Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen
2003	J	`jnl`	WATSON: design space boundary exploration and model generation for analog and RFIC design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bart De Smedt, Georges G. E. Gielen
2002	—	`conf`	A 8-bit 200 MS/s interpolating/averaging CMOS A/D converter. CICC Jan Vandenbussche, Koen Uyttenhove, Erik Lauwers, Michel S. J. Steyaert, Georges G. E. Gielen
2002	A	`conf`	A Fitting Approach to Generate Symbolic Expressions for Linear and Nonlinear Analog Circuit Performance Characteristics. DATE Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen
2002	A	`conf`	A behavioral simulation tool for continuous-time delta sigma modulators. ICCAD Kenneth Francken, Martin Vogels, Ewout Martens, Georges G. E. Gielen
2002	J	`jnl`	A fast learning algorithm for time-delay neural networks. Inf. Sci. Minghu Jiang, Georges G. E. Gielen, Beixing Deng, Xiaoyan Zhu
2002	J	`jnl`	A layout synthesis methodology for array-type analog blocks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Geert Van der Plas, Jan Vandenbussche, Georges G. E. Gielen, Willy M. C. Sansen
2002	A*	`conf`	An efficient optimization--based technique to generate posynomial performance models for analog integrated circuits. DAC Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen
2002	A*	`conf`	Behavioral modeling of (coupled) harmonic oscillators. DAC Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen
2002	J	`jnl`	Braille to print translations for Chinese. Inf. Softw. Technol. Minghu Jiang, Xiaoyan Zhu, Georges G. E. Gielen, Elliott Drábek, Ying Xia, Gang Tan, Ta Bao
2002	J	`jnl`	CYCLONE: automated design and layout of RF LC-oscillators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Carl De Ranter, Geert Van der Plas, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen
2002	J	`jnl`	Circuit simplification for the symbolic analysis of analogintegrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen
2002	A*	`conf`	Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients. DAC Mustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen
2002	A	`conf`	Constructing Symbolic Models for the Input/Output Behavior of Periodically Time-Varying Systems Using Harmonic Transfer Matrices. DATE Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen
2002	A	`conf`	DAISY-CT: A High-Level Simulation Tool for Continuous-Time Delta Sigma Modulators. DATE Kenneth Francken, Martin Vogels, Ewout Martens, Georges G. E. Gielen
2002	J	`jnl`	Editorial. Integr. Georges G. E. Gielen
2002	—	`conf`	Efficient time-domain simulation of continuous-time Delta-Sigma A/D converters using analytical integration. ISCAS (4) Martin Vogels, Kenneth Francken, Ewout Martens, Georges G. E. Gielen
2002	J	`jnl`	Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits. IEEE J. Solid State Circuits Mustafa Badaroglu, Marc van Heijningen, Vincent Gravot, John Compiet, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man
2002	A	`conf`	On the difference between two widely publicized methods for analyzing oscillator phase behavior. ICCAD Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen
2002	A*	`conf`	Optimal design of delta-sigma ADCs by design space exploration. DAC Ovidiu Bajdechi, Johan H. Huijsing, Georges G. E. Gielen
2002	J	`jnl`	Power estimation methods for analog circuits for architectural exploration of integrated systems. IEEE Trans. Very Large Scale Integr. Syst. Erik Lauwers, Georges G. E. Gielen
2002	—	`conf`	Power optimization in ΣΔ ADC design. DSP Ovidiu Bajdechi, Johan H. Huijsing, Georges G. E. Gielen
2002	—	`conf`	Regression criteria and their application in different modeling cases. ISCAS (5) Francky Leyn, Erik Lauwers, Martin Vogels, Georges G. E. Gielen, Willy M. C. Sansen
2002	J	`jnl`	Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification. IEEE J. Solid State Circuits Marc van Heijningen, Mustafa Badaroglu, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man
2002	J	`jnl`	Symbolic modeling of periodically time-varying systems usingharmonic transfer matrices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen
2002	A	`conf`	Systematic Design of a 200 Ms/S 8-bit Interpolating A/D Converter. DATE Jan Vandenbussche, Erik Lauwers, Koen Uyttenhove, Michiel Steyaert, Georges G. E. Gielen
2002	A*	`conf`	Systematic design of a 200 MS/s 8-bit interpolating/averaging A/D converter. DAC Jan Vandenbussche, Koen Uyttenhove, Erik Lauwers, Michiel Steyaert, Georges G. E. Gielen
2002	—	`conf`	WATSON: a multi-objective design space exploration tool for analog and RF IC design. CICC Bart De Smedt, Georges G. E. Gielen
2001	J	`jnl`	A CMOS multiparameter biochemical microsensor with temperature control and signal interfacing. IEEE J. Solid State Circuits Erik Lauwers, Jan Suls, Walter Gumbrecht, David Maes, Georges G. E. Gielen, Willy Sansen
2001	A	`conf`	A Layout-Aware Synthesis Methodology for RF Circuits. ICCAD Peter J. Vancorenland, Geert Van der Plas, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen
2001	J	`jnl`	AMGIE-A synthesis environment for CMOS analog integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Geert Van der Plas, Geert Debyser, Francky Leyn, Koen Lampaert, Jan Vandenbussche, Georges G. E. Gielen, Willy M. C. Sansen, Petar Veselinovic, Domine Leenaerts
2001	—	`conf`	Dedicated system-level simulation of ΔΣ modulators. CICC Kenneth Francken, Martin Vogels, Georges G. E. Gielen
2001	A	`conf`	Design challenges and emerging EDA solutions in mixed-signal IC design. DATE Georges G. E. Gielen
2001	A*	`conf`	Efficient DDD-based Symbolic Analysis of Large Linear Analog Circuits. DAC Wim Verhaegen, Georges G. E. Gielen
2001	A	`conf`	Efficient time-domain simulation of telecom frontends using a complex damped exponential signal model. DATE Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen
2001	A	`conf`	Embedded Tutorial: CAD Solutions and Outstanding Challenges for Mixed-Signal and RF IC Design. ICCAD Domine Leenaerts, Rob A. Rutenbar, Georges G. E. Gielen
2001	A	`conf`	High-level simulation of substrate noise generation from large digital circuits with multiple supplies. DATE Mustafa Badaroglu, Marc van Heijningen, Vincent Gravot, Stéphane Donnay, Hugo De Man, Georges G. E. Gielen, Marc Engels, Ivo Bolsens
2001	A*	`conf`	Panel: When Will the Analog Design Flow Catch Up with Digital Methodology? DAC Georges G. E. Gielen, Mike Sottak, Mike Murray, Linda Kaye, Maria del Mar Hershenson, Kenneth S. Kundert, Philippe Magarshack, Akria Matsuzawa, Ronald A. Rohrer, Ping Yang
2001	A	`conf`	Simulation-Based Automatic Generation of Signomial and Posynomial Performance Models for Analog Integrated Circuit Sizing. ICCAD Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen
2000	A	`conf`	ACTIF: A High-Level Power Estimation Tool for Analog Continuous-Time-Filters. ICCAD Erik Lauwers, Georges G. E. Gielen
2000	A*	`conf`	CYCLONE: automated design and layout of RF LC-oscillators. DAC Carl De Ranter, Bram De Muer, Geert Van der Plas, Peter J. Vancorenland, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen
2000	J	`jnl`	Computer-aided design of analog and mixed-signal integrated circuits. Proc. IEEE Georges G. E. Gielen, Rob A. Rutenbar
2000	A	`conf`	DAISY: A Simulation-Based High-Level Synthesis Tool for Delta-Sigma Modulators. ICCAD Kenneth Francken, Peter J. Vancorenland, Georges G. E. Gielen
2000	C	`conf`	Efficient analysis of the stability of sigma-delta modulators using wavelets. ISCAS Martin Vogels, Georges G. E. Gielen
2000	—	`conf`	High-Level Design Case of a Switched-Capacitor Low-Pass Filter Using Verilog-A. BMAS Erik Lauwers, Georges G. E. Gielen, Koen Lampaert, Paolo Miliozzi
2000	—	`conf`	Modeling and Simulation of a Sigma-Delta Digital to Analog Converter Using VHDL-AMS. BMAS Martin Vogels, Bart De Smedt, Georges G. E. Gielen
2000	A*	`conf`	Optimal RF design using smart evolutionary algorithms. DAC Peter J. Vancorenland, Carl De Ranter, Michiel Steyaert, Georges G. E. Gielen
2000	A*	`conf`	Survival strategies for mixed-signal systems-on-chip (panel session). DAC Stephan Ohr, Rob A. Rutenbar, Henry Chang, Georges G. E. Gielen, Rudolf Koch, Roy McGuffin, K. C. Murphy
2000	A*	`conf`	Systematic design of a 14-bit 150-MS/s CMOS current-steering D/A converter. DAC Geert Van der Plas, Jan Vandenbussche, Walter Daems, Antal van den Bosch, Georges G. E. Gielen, Willy M. C. Sansen
1999	J	`jnl`	A 14-bit intrinsic accuracy Q IEEE J. Solid State Circuits Geert Van der Plas, Jan Vandenbussche, Willy Sansen, Michel S. J. Steyaert, Georges G. E. Gielen
1999	A	`conf`	A Power Estimation Model for High-Speed CMOS A/D Converters. DATE Erik Lauwers, Georges G. E. Gielen
1999	—	`conf`	BANDIT: embedding analog-to-digital converters on digital telecom ASICs. ICECS Stéphane Donnay, Marc van Heijningen, Mustafa Badaroglu, Wim Diels, Marc Engels, Ivo Bolsens, Yann A. Zinzius, Georges G. E. Gielen, Willy Sansen, Tony Fondén, Svante Signell
1999	A*	`conf`	Circuit Complexity Reduction for Symbolic Analysis of Analog Integrated Circuits. DAC Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen
1999	—	`conf`	High-level simulation and power modelling of mixed-signal front-ends for digital telecommunications. ICECS Piet Wambacq, Gerd Vandersteen, Stéphane Donnay, Marc Engels, Ivo Bolsens, Erik Lauwers, Piet Vanassche, Georges G. E. Gielen
1999	—	`conf`	Methodology for analog technology porting including performance tuning. ISCAS (1) Kenneth Francken, Georges G. E. Gielen
1999	—	`conf`	Statistical behavioral modeling for A/D-converters. ICECS Geert Van der Plas, Jan Vandenbussche, Wim Verhaegen, Georges G. E. Gielen, Willy Sansen
1998	—	`conf`	A 12 bit 200 MHz low glitch CMOS D/A converter. CICC Anne Van den Bosch, Marc Borremans, Jan Vandenbussche, Geert Van der Plas, Augusto Manuel Marques, José Bastos, Michiel Steyaert, Georges G. E. Gielen, Willy Sansen
1998	A	`conf`	An efficient DC root solving algorithm with guaranteed convergence for analog integrated CMOS circuits. ICCAD Francky Leyn, Georges G. E. Gielen, Willy M. C. Sansen
1998	—	`conf`	Behavioral model for D/A converters as VSI virtual components. CICC Jan Vandenbussche, Geert Van der Plas, Georges G. E. Gielen, Michiel Steyaert, Willy Sansen
1998	A	`conf`	Efficient analog circuit synthesis with simultaneous yield and robustness optimization. ICCAD Geert Debyser, Georges G. E. Gielen
1998	—	`conf`	Efficient symbolic analysis of analog integrated circuits using determinant decision diagrams. ICECS Wim Verhaegen, Georges G. E. Gielen
1998	A	`conf`	Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon. DATE Jan Vandenbussche, Stéphane Donnay, Francky Leyn, Georges G. E. Gielen, Willy M. C. Sansen
1998	J	`jnl`	High-Level Power Minimization of Analog Sensor Interface Architectures. Integr. Comput. Aided Eng. Stéphane Donnay, Georges G. E. Gielen, Willy M. C. Sansen
1998	—	`conf`	Modeling and simulation for low power in mixed-signal integrated systems. CICC Georges G. E. Gielen
1998	—	`conf`	Mondriaan: a tool for automated layout synthesis of array-type analog blocks. CICC Geert Van der Plas, Jan Vandenbussche, Georges G. E. Gielen, Willy Sansen
1998	—	`conf`	Nonlinear behavioral modeling and phase noise evaluation in phase locked loops. CICC Bart De Smedt, Georges G. E. Gielen
1998	J	`jnl`	Probabilistic fault detection and the selection of measurements for analog integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhihua Wang, Georges G. E. Gielen, Willy M. C. Sansen
1998	—	`conf`	Transforming small-signal modeling into control system modeling. CICC Francky Leyn, Willy Sansen, Georges G. E. Gielen
1997	A	`conf`	A behavioral signal path modeling methodology for qualitative insight in and efficient sizing of CMOS opamps. ICCAD Francky Leyn, Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen
1997	Misc	`conf`	Automated test pattern generation for analog integrated circuits. VTS Wim Verhaegen, Geert Van der Plas, Georges G. E. Gielen
1997	—	`conf`	High-level synthesis of analog sensor interface front-ends. ED&TC Stéphane Donnay, Georges G. E. Gielen, Willy M. C. Sansen, Wim Kruiskamp, Domine Leenaerts, W. van Bokhoven
1996	—	`conf`	ADMIRE: advanced mixed signal design environment. ICECS Philippe Reynaert, Ludwig G. A. Callewaert, Georges G. E. Gielen, Geert Debyser, Koen Lampaert, Francky Leyn, Geert Van der Plas, Willy Sansen, Birger Schneider, René Bloch, Dave Orton, Steve Boardman, Jeremy Stent, Jean-François Agaësse, Jörg-Olliver Fischer-Binder, Jukka Riihiaho, Kari Tukkiniemi
1996	A*	`conf`	Synthesis Tools for Mixed-Signal ICs: Progress on Frontend and Backend Strategies. DAC L. Richard Carley, Georges G. E. Gielen, Rob A. Rutenbar, Willy M. C. Sansen
1995	—	`conf`	A flexible topology selection program as part of an analog synthesis system. ED&TC Petar Veselinovic, Domine Leenaerts, W. van Bokhoven, Francky Leyn, F. Proesmans, Georges G. E. Gielen, Willy Sansen
1995	A	`conf`	A high-level design and optimization tool for analog RF receiver front-ends. ICCAD Jan Crols, Stéphane Donnay, Michiel Steyaert, Georges G. E. Gielen
1995	J	`jnl`	A performance-driven placement tool for analog integrated circuits. IEEE J. Solid State Circuits Koen Lampaert, Georges G. E. Gielen, Willy M. C. Sansen
1995	J	`jnl`	An analogue module generator for mixed analogue/digital asic design. Int. J. Circuit Theory Appl. Georges G. E. Gielen, Geert Debyser, Koen Lampaert, Francky Leyn, Koen Swings, Geert Van der Plas, Willy Sansen, Domine Leenaerts, Petar Veselinovic, W. van Bokhoven
1995	A*	`conf`	Direct Performance-Driven Placement of Mismatch-Sensitive Analog Circuits. DAC Koen Lampaert, Georges G. E. Gielen, Willy M. C. Sansen
1995	J	`jnl`	Efficient symbolic computation of approximated small-signal characteristics of analog integrated circuits. IEEE J. Solid State Circuits Piet Wambacq, Francisco V. Fernández, Georges G. E. Gielen, Willy Sansen, Ángel Rodríguez-Vázquez
1995	C	`conf`	Use of Symbolic Analysis in Analog Circuit Synthesis. ISCAS Georges G. E. Gielen, Geert Debyser, Piet Wambacq, Koen Swings, Willy M. C. Sansen
1994	—	`conf`	A Methodology for Analog Design Automation in Mixed-Signal ASICs. EDAC-ETC-EUROASIC Stéphane Donnay, Koen Swings, Georges G. E. Gielen, Willy M. C. Sansen, Wim Kruiskamp, Domine Leenaerts
1994	C	`conf`	A Novel Method for the Fault Detection of Analog Integrated Circuits. ISCAS Zhihua Wang, Georges G. E. Gielen, Willy M. C. Sansen
1994	A	`conf`	Fault detection and input stimulus determination for the testing of analog integrated circuits based on power-supply current monitoring. ICCAD Georges G. E. Gielen, Zhihua Wang, Willy M. C. Sansen
1994	C	`conf`	Pleasures, Perils and Pitfalls of Symbolic Analysis. ISCAS Francisco V. Fernández, Georges G. E. Gielen, Lawrence Huelsman, Agnieszka Konczykowska, Stefano Manetti, Willy M. C. Sansen, Jirí Vlach
1994	C	`conf`	Symbolic Analysis of Large Analog Integrated Circuits by Approximation During Expression Generation. ISCAS Francisco V. Fernández, Piet Wambacq, Georges G. E. Gielen, Ángel Rodríguez-Vázquez, Willy M. C. Sansen
1994	J	`jnl`	Symbolic analysis methods and applications for analog circuits: a tutorial overview. Proc. IEEE Georges G. E. Gielen, Piet Wambacq, Willy M. C. Sansen
1993	C	`conf`	Modeling of the Power-supply Interactions of CMOS Operational Amplifiers Using Symbolic Computation. ISCAS Georges G. E. Gielen, Willy M. C. Sansen
1991	A	`conf`	A Behavioral Representation for Nyquist Rate A/D Converters. ICCAD Edward W. Y. Liu, Alberto L. Sangiovanni-Vincentelli, Georges G. E. Gielen, Paul R. Gray
1991	—	`conf`	Interactive symbolic distortion analysis of analogue integrated circuits. EURO-DAC Piet Wambacq, Georges G. E. Gielen, Willy Sansen
1991	—	`book`	Symbolic analysis for automated design of analog integrated circuits. Georges G. E. Gielen, Willy M. C. Sansen
1990	—	`conf`	An intelligent design system for analogue integrated circuits. EURO-DAC Georges G. E. Gielen, Koen Swings, Willy M. C. Sansen
1990	J	`jnl`	Analog circuit design optimization based on symbolic simulation and simulated annealing. IEEE J. Solid State Circuits Georges G. E. Gielen, Herman C. C. Walscharts, Willy M. C. Sansen
1989	J	`jnl`	ISAAC: a symbolic simulator for analog integrated circuits. IEEE J. Solid State Circuits Georges G. E. Gielen, Herman C. C. Walscharts, Willy M. C. Sansen