George Theodoridis

77 papers A 5B 1C 7Misc 1Journal 30Unranked 33

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Exploiting temporal parallelism for LSTM Autoencoder acceleration on FPGA. CoRR Aimilios Leftheriotis, Dimosthenis Masouros, Dimitrios Soudris, George Theodoridis
2025	J	`jnl`	Efficient Majority Logic Parallel-Prefix Adder Design. IEEE Access Constantinos Efstathiou, Ioannis Kouretas, Paris Kitsos, George Theodoridis
2025	A	`conf`	Multi-Partner Project: Secure Hardware Accelerated Data Analytics for 6G Networks: The PRIVATEER Approach. DATE Ilias Papalamprou, Aimilios Leftheriotis, Apostolis Garos, Georgios Gardikis, Maria Christopoulou, George Xilouris, Lampros Argyriou, Antonia Karamatskou, Nikolaos Papadakis, Emmanouil Kalotychos, Nikolaos Chatzivasileiadis, Dimosthenis Masouros, George Theodoridis, Dimitrios Soudris
2025	—	`conf`	PRIVATEER: Secure FPGA Acceleration for 6G AI Edge Analytics. ISVLSI Aimilios Leftheriotis, Ilias Papalamprou, Apostolos Garos, Georgios Gardikis, Maria Christopoulou, George Xilouris, Georgios Livanos, Nikolaos Papadakis, Dimosthenis Masouros, George Theodoridis, Dimitrios Soudris
2023	—	`conf`	Evaluating Versal ACAP and conventional FPGA platforms for AI inference. MOCAST Aimilios Leftheriotis, Aphrodite Tzomaka, Dimitrios Danopoulos, George Lentaris, George Theodoridis, Dimitrios Soudris
2022	C	`conf`	A Multi-stage Hybrid Approach for Mapping Applications on Heterogeneous Multi-core Platforms. VLSI-SoC Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis, Nikos S. Voros
2022	C	`conf`	An FPGA implementation of the VESA Display Stream Compression decoder. VLSI-SoC Nikolaos Kefalas, George Theodoridis
2020	C	`conf`	Exploring the FPGA Implementations of the LBlock, Piccolo, Twine, and Klein Ciphers. VLSI-SOC S. Moraitis, D. Seitanidis, George Theodoridis, Odysseas G. Koufopavlou
2019	—	`conf`	Implementing VESA Display Stream Compression Encoder in FPGAs. PATMOS Nikolaos Kefalas, George Theodoridis
2019	J	`jnl`	Low-memory and high-performance architectures for the CCSDS 122.0-B-1 compression standard. Integr. Nikolaos Kefalas, George Theodoridis
2018	—	`conf`	A High Performance Bitplane Encoder for the CCSDS 122.0-B-1 Compression Standard. TSP Nikolaos Kefalas, George Theodoridis
2018	—	`conf`	Mapping and Scheduling Hard Real Time Applications on Multicore Systems - The ARGO Approach. ARC Panayiotis Alefragis, George Theodoridis, Merkourios Katsimpris, Christos Valouxis, Christos Gogos, George Goulas, Nikolaos S. Voros, Simon Reder, Koray Kasnakli, Marcus Bednara, David Müller, Umut Durak, Jürgen Becker
2018	J	`jnl`	Static Mapping of Applications on Heterogeneous Multi-Core Platforms Combining Logic-Based Benders Decomposition with Integer Linear Programming. ACM Trans. Design Autom. Electr. Syst. Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis, Nikos S. Voros
2017	—	`conf`	High-throughput FPGA implementation of the CCSDS 122.0-B-1 compression standard. PATMOS Nikolaos Kefalas, George Theodoridis
2017	—	`conf`	Task graph mapping and scheduling on heterogeneous architectures under communication constraints. SAMOS Andreas Emeretlis, T. Tsakoulis, George Theodoridis, Panayiotis Alefragis, Nikos S. Voros
2016	J	`jnl`	A Logic-Based Benders Decomposition Approach for Mapping Applications on Heterogeneous Multicore Platforms. ACM Trans. Embed. Comput. Syst. Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis, Nikolaos S. Voros
2016	—	`conf`	A hybrid approach for mapping and scheduling on heterogeneous multicore systems. SAMOS Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis, Nikolaos S. Voros
2016	J	`jnl`	Area-Throughput Trade-Offs for SHA-1 and SHA-256 Hash Functions' Pipelined Designs. J. Circuits Syst. Comput. Harris E. Michail, George Athanasiou, Vasilios I. Kelefouras, George Theodoridis, Thanos Stouraitis, Costas E. Goutis
2016	J	`jnl`	Design and implementation of totally-self checking SHA-1 and SHA-256 hash functions' architectures. Microprocess. Microsystems Harris E. Michail, Georgios Athanasiou, George Theodoridis, Andreas Gregoriades, Costas E. Goutis
2015	—	`conf`	40 Gb/s FPGA implementation of a reduced complexity volterra DFE for DQPSK optical links. ICTON Maki Nanou, Andreas Emeretlis, Christina Tanya Politi, George Theodoridis, Kristina Georgoulakis, George-Othon Glentis
2015	J	`jnl`	A high performance 5 stage pipeline architecture for the H.264/AVC deblocking filter. Integr. Nikolaos Kefalas, George Theodoridis
2015	—	`conf`	A parallel luma-chroma filtering architecture for H.264/AVC deblocking filter. ICCE-Berlin Nikolaos Kefalas, George Theodoridis
2015	—	`conf`	FPGA implementation of a MIMO DFE IN 40 GB/S DQPSK optical links. EUSIPCO Andreas Emeretlis, V. Kefelouras, George Theodoridis, Maki Nanou, Christina Tanya Politi, Kristina Georgoulakis, George-Othon Glentis
2015	—	`conf`	Mapping DAGs on Heterogeneous Platforms Using Logic-Based Benders Decompostion. ISVLSI Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis, Nikos S. Voros
2014	—	`conf`	A Hybrid ILP-CP Model for Mapping Directed Acyclic Task Graphs to Multicore Architectures. IPDPS Workshops Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis, Nikolaos S. Voros
2014	—	`conf`	An 8K-UHD capable 8-stage pipeline deblocking filter for H.264/AVC. ISCCSP Nikolaos Kefalas, George Theodoridis
2014	—	`conf`	FPGA Implementations for Volterra DFEs. Panhellenic Conference on Informatics Andreas Emeretlis, George Theodoridis
2014	—	`conf`	High-performance FPGA implementations of volterra DFEs for optical fiber systems. ReConFig Andreas Emeretlis, George Theodoridis, George-Othon Glentis
2014	J	`jnl`	On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs. Integr. Harris E. Michail, Georgios Athanasiou, George Theodoridis, Costas E. Goutis
2014	J	`jnl`	Optimising the SHA-512 cryptographic hash function on FPGAs. IET Comput. Digit. Tech. Georgios Athanasiou, Harris E. Michail, George Theodoridis, Costas E. Goutis
2013	J	`jnl`	A Systematic Flow for Developing Totally Self-Checking Architectures for SHA-1 and SHA-2 Cryptographic Hash Families. J. Circuits Syst. Comput. George Athanasiou, George Theodoridis, Costas E. Goutis, Harris E. Michail, Takis Kasparis
2013	J	`jnl`	High-performance FPGA implementations of the cryptographic hash function JH. IET Comput. Digit. Tech. George Athanasiou, Harris E. Michail, George Theodoridis, Costas E. Goutis
2012	C	`conf`	High-throughput Hardware Architectures of the JH Round-three SHA-3 Candidate - An FPGA Design and Implementation Approach. SECRYPT George Athanasiou, Chara I. Chalkou, D. Bardis, Harris E. Michail, George Theodoridis, Costas E. Goutis
2012	C	`conf`	On the Development of Totally Self-checking Hardware Design for the SHA-1 Hash Function. SECRYPT Harris E. Michail, George Athanasiou, Andreas Gregoriades, George Theodoridis, Costas E. Goutis
2012	J	`jnl`	On the exploitation of a high-throughput SHA-256 FPGA design for HMAC. ACM Trans. Reconfigurable Technol. Syst. Harris E. Michail, George Athanasiou, Vasilios I. Kelefouras, George Theodoridis, Costas E. Goutis
2010	—	`conf`	A high throughput pipelined architecture for H.264/AVC deblocking filter. ICECS Nikolaos Kefalas, George Theodoridis
2009	J	`jnl`	An Application Development Framework for ARISE Reconfigurable Processors. ACM Trans. Reconfigurable Technol. Syst. Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis
2009	J	`jnl`	An integer linear programming model for mapping applications on hybrid systems. IET Comput. Digit. Tech. George Theodoridis, Nikolaos Vassiliadis, Spiridon Nikolaidis
2009	J	`jnl`	The ARISE Approach for Extending Embedded Processors With Arbitrary Hardware Accelerators. IEEE Trans. Very Large Scale Integr. Syst. Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis
2008	—	`conf`	ARISE Machines: Extending Processors with Hybrid Accelerators. ARC Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis
2007	J	`jnl`	A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms CoRR Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
2007	J	`jnl`	Automated framework for partitioning DSP applications in hybrid reconfigurable platforms. Microprocess. Microsystems Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
2007	—	`conf`	The ARISE Reconfigurable Instruction Set Extensions Framework. ICSAMOS Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis
2006	J	`jnl`	A high-performance data path for synthesizing DSP kernels. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Constantinos E. Goutis
2006	A	`conf`	An automated development framework for a RISC processor with reconfigurable instruction set extensions. IPDPS Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis
2006	—	`conf`	Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode Support. ARC Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis
2006	J	`jnl`	High-Speed FPGA Implementation of Secure Hash Algorithm for IPSec and VPN Applications. J. Supercomput. Athanasios Kakarountas, Haralambos Michail, Athanasios Milidonis, Costas E. Goutis, George Theodoridis
2006	J	`jnl`	Power Management Through Dynamic Frequency Scaling for Low and Medium Bit-Rate Digital Receivers. J. Low Power Electron. Athanasios Kakarountas, Nikolaos D. Zervas, George Theodoridis, Haralambos Michail, Dimitrios Soudris
2005	A	`conf`	A Framework for Partitioning Computational Intensive Applications in Hybrid Reconfigurable Platforms. IPDPS Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
2005	J	`jnl`	A Reconfigurable Coarse-grain Data-path for Accelerating Computational Intensive Kernels. J. Circuits Syst. Comput. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Constantinos E. Goutis
2005	J	`jnl`	A method for partitioning applications in hybrid reconfigurable architectures. Des. Autom. Embed. Syst. Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Costas E. Goutis
2005	—	`conf`	A methodology for partitioning DSP applications in hybrid reconfigurable systems. ISCAS (2) Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
2005	J	`jnl`	Behavioral-level event-driven power management for DECT digital receivers. Microelectron. J. Nikolaos D. Zervas, George Theodoridis, Dimitrios Soudris
2004	J	`jnl`	A Framework for Data Partitioning for C++ Data-Intensive Applications. Des. Autom. Embed. Syst. Athanasios Milidonis, Gregory Dimitroulakos, Michalis D. Galanis, Athanasios P. Kakarountas, George Theodoridis, Constantinos E. Goutis, Francky Catthoor
2004	—	`conf`	A Novel Constant-Time Fault-Secure Binary Counter. PATMOS Dimitris Karatasos, Athanasios Kakarountas, George Theodoridis, Constantinos E. Goutis
2004	—	`conf`	A Novel Data-Path for Accelerating DSP Kernels. SAMOS Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Costas E. Goutis
2004	A	`conf`	A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms. DATE Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
2004	—	`conf`	A high performance data-path to accelerate DSP kernels. ICECS Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Costas E. Goutis
2004	A	`conf`	A novel coarse-grain reconfigurable data-path for accelerating DSP kernels. FPGA Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
2004	Misc	`conf`	Accelerating DSP Applications on a Mixed Granularity Platform with a New Reconfigurable Coarse-Grain Data-Path. FCCM Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
2004	C	`conf`	An Automated C++ Code and Data Partitioning Framework for Data Management of Data-Intensive Applications. SCOPES Athanasios Milidonis, Grigoris Dimitroulakos, Michalis D. Galanis, George Theodoridis, Constantinos E. Goutis, Francky Catthoor
2004	—	`conf`	Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path. PATMOS Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
2004	B	`conf`	Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path. FPL Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
2003	—	`conf`	A novel high-speed counter with counting rate independent of the counter's length. ICECS Athanasios P. Kakarountas, George Theodoridis, Kyriakos S. Papadomanolakis, Costas E. Goutis
2003	J	`jnl`	An efficient reconfigurable multiplier architecture for Galois field GF(2 Microelectron. J. Paris Kitsos, George Theodoridis, Odysseas G. Koufopavlou
2003	—	`conf`	An reconfigurable multiplier in GF(2 ICECS Paris Kitsos, George Theodoridis, Odysseas G. Koufopavlou
2003	—	`conf`	Power aware data type refinement on the HIPERLAN/2. ICECS Gregory Dimitroulakos, Athanasios Milidonis, Michalis D. Galanis, George Theodoridis, Costas E. Goutis, Francky Catthoor
2002	J	`jnl`	A fast and accurate delay dependent method for switching estimation of large combinational circuits. J. Syst. Archit. S. Theoharis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis, Adonios Thanailakis
2001	J	`jnl`	A Fast and Accurate Method of Power Estimation for Logic Level Networks. VLSI Design George Theodoridis, S. Theoharis, Dimitrios Soudris, Constantinos E. Goutis
2001	J	`jnl`	A Probabilistic Power Estimation Method for Combinational Circuits Under Real Gate Delay Model. VLSI Design George Theodoridis, Spyros Theoharis, Dimitrios Soudris, Constantinos E. Goutis
2000	—	`conf`	Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions. PATMOS George Theodoridis, S. Theoharis, Nikolaos D. Zervas, Constantinos E. Goutis
2000	C	`conf`	Low power design of a multi-mode transceiver. ISCAS Dimitrios Soudris, Minas Perakis, Haris Mizas, Vasilios A. Mardiris, Kosfas Katis, Chrissavgi Dre, A. E. Tzimas, E. G. Metaxakis, Grigorios Kalivas, Nikolaos D. Zervas, Spyros Theoharis, George Theodoridis, Adonios Thanailakis, Constantinos E. Goutis
2000	—	`conf`	Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers. PATMOS Nikolaos D. Zervas, S. Theoharis, Athanasios Kakarountas, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
1999	J	`jnl`	A New Method for Low Power Design of Two-Level Logic Circuits. VLSI Design George Theodoridis, Spyros Theoharis, Dimitrios Soudris, Constantinos E. Goutis
1999	—	`conf`	An efficient probabilistic method for logic circuits using real delay gate model. ISCAS (1) George Theodoridis, S. Theoharis, Dimitrios Soudris, Thanos Stouraitis, Constantinos E. Goutis
1996	—	`conf`	A novel approach for reducing the switching activity in two-level logic circuits. ICECS George Theodoridis, S. Theoharis, Dimitrios Soudris, Odysseas G. Koufopavlou, Costas E. Goutis
1996	—	`conf`	Low-power design of array architectures. ICECS Dimitrios Soudris, George Theodoridis, S. Theoharis, Adonios Thanailakis