George Michelogiannakis

61 papers A* 5A 7B 4C 9Misc 2Journal 17Unranked 17

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	A Novel 1-Bit Adder Cell and Filters for Oversampling Superconducting ADCs. LASCAS Patricia Gonzalez-Guerrero, Panagiotis Zarkos, Carl Grace, George Michelogiannakis
2026	J	`jnl`	A-Graph: A Unified Graph Representation for At-Will Simulation across System Stacks. CoRR Daniel Price, Prabhu Vellaisamy, Patricia Gonzalez, George Michelogiannakis, John Paul Shen, Di Wu
2025	C	`conf`	Enabling Classical-Quantum Interface Using Digital SFQ for Pulse-Phase Driven Control for Superconducting Qubits. ISCAS Meriam Gay Bautista-Jurney, Patricia Gonzalez-Guerrero, George Michelogiannakis, Anastasiia Butko
2024	J	`jnl`	Area Efficient Asynchronous SFQ Pulse Round-Robin Distribution Network. IEEE Trans. Circuits Syst. I Regul. Pap. Meriam Gay Bautista, Darren Lyles, Kylie Huch, Patricia Gonzalez-Guerrero, George Michelogiannakis
2024	C	`conf`	Job Scheduling in High Performance Computing Systems with Disaggregated Memory Resources. CLUSTER Jie Li, George Michelogiannakis, Samuel A. Maloney, Brandon Cook, Estela Suarez, John Shalf, Yong Chen
2024	—	`conf`	Scheduling and Allocation of Disaggregated Memory Resources in HPC Systems. IPDPS (Workshops) Jie Li, George Michelogiannakis, Brandon Cook, John Shalf, Yong Chen
2024	J	`jnl`	Toward Practical Superconducting Accelerators for Machine Learning Using U-SFQ. ACM J. Emerg. Technol. Comput. Syst. Patricia Gonzalez-Guerrero, Kylie Huch, Nirmalendu Patra, Doru-Thom Popovici, George Michelogiannakis
2023	—	`conf`	An Area Efficient Superconducting Unary CNN Accelerator. ISQED Patricia Gonzalez-Guerrero, Kylie Huch, Nirmalendu Patra, Doru-Thom Popovici, George Michelogiannakis
2023	J	`jnl`	Analyzing Resource Utilization in an HPC System: A Case Study of NERSC Perlmutter. CoRR Jie Li, George Michelogiannakis, Brandon Cook, Dulanya Cooray, Yong Chen
2023	C	`conf`	Analyzing Resource Utilization in an HPC System: A Case Study of NERSC's Perlmutter. ISC Jie Li, George Michelogiannakis, Brandon Cook, Dulanya Cooray, Yong Chen
2023	C	`conf`	Efficient Intra-Rack Resource Disaggregation for HPC Using Co-Packaged DWDM Photonics. CLUSTER George Michelogiannakis, Yehia Arafa, Brandon Cook, Liang Yuan Dai, Abdel-Hameed A. Badawy, Madeleine Glick, Yuyang Wang, Keren Bergman, John Shalf
2023	J	`jnl`	Efficient Intra-Rack Resource Disaggregation for HPC Using Co-Packaged DWDM Photonics. CoRR George Michelogiannakis, Yehia Arafa, Brandon Cook, Liang Yuan Dai, Abdel-Hameed A. Badawy, Madeleine Glick, Yuyang Wang, Keren Bergman, John Shalf
2023	—	`conf`	MC-ELMM: Multi-Chip Endurance-Limited Memory Management. MEMSYS Andrew M. Bartolo, Mohamed M. Sabry Aly, George Michelogiannakis, Subhasish Mitra
2023	A	`conf`	Reliable Hyperdimensional Reasoning on Unreliable Emerging Technologies. ICCAD Hamza Errahmouni Barkam, Sanggeon Yun, Hanning Chen, Paul Gensler, Albi Mema, Andrew Ding, George Michelogiannakis, Hussam Amrouch, Mohsen Imani
2023	J	`jnl`	Superconducting Shuttle-Flux Shift Register for Race Logic and Its Applications. IEEE Trans. Circuits Syst. I Regul. Pap. Meriam Gay Bautista, Patricia Gonzalez-Guerrero, Darren Lyles, George Michelogiannakis
2022	J	`jnl`	A Case For Intra-rack Resource Disaggregation in HPC. ACM Trans. Archit. Code Optim. George Michelogiannakis, Benjamin Klenk, Brandon Cook, Min Yee Teh, Madeleine Glick, Larry Dennison, Keren Bergman, John Shalf
2022	—	`conf`	Establishing Cooperative Computation with Hardware Embassies. SEED Alvin Oliver Glova, Yukai Yang, Yiyao Wan, Zhizhou Zhang, George Michelogiannakis, Jonathan Balkind, Timothy Sherwood
2022	J	`jnl`	PaST-NoC: A Packet-Switched Superconducting Temporal NoC. CoRR Darren Lyles, Patricia Gonzalez-Guerrero, Meriam Gay Bautista, George Michelogiannakis
2022	—	`conf`	Superconducting Digital DIT Butterfly Unit for Fast Fourier Transform Using Race Logic. NEWCAS Meriam Gay Bautista, Patricia Gonzalez-Guerrero, Darren Lyles, Kylie Huch, George Michelogiannakis
2022	A*	`conf`	Temporal and SFQ pulse-streams encoding for area-efficient superconducting accelerators. ASPLOS Patricia Gonzalez-Guerrero, Meriam Gay Bautista, Darren Lyles, George Michelogiannakis
2021	A	`conf`	SRNoC: A Statically-Scheduled Circuit-Switched Superconducting Race Logic NoC. IPDPS George Michelogiannakis, Darren Lyles, Patricia Gonzalez-Guerrero, Meriam Gay Bautista, Dilip Vasudevan, Anastasiia Butko
2021	—	`conf`	Superconducting Shuttle-flux Shift Buffer for Race Logic. MWSCAS Meriam Gay Bautista, Patricia Gonzalez-Guerrero, Darren Lyles, George Michelogiannakis
2021	J	`jnl`	Temporal Computing With Superconductors. IEEE Micro Georgios Tzimpragos, Jennifer Volk, Dilip Vasudevan, Nestan Tsiskaridze, George Michelogiannakis, Advait Madhavan, John Shalf, Timothy Sherwood
2020	A*	`conf`	A Computational Temporal Logic for Superconducting Accelerators. ASPLOS Georgios Tzimpragos, Dilip Vasudevan, Nestan Tsiskaridze, George Michelogiannakis, Advait Madhavan, Jennifer Volk, John Shalf, Timothy Sherwood
2020	J	`jnl`	Language Support for Navigating Architecture Design in Closed Form. ACM J. Emerg. Technol. Comput. Syst. Weilong Cui, Georgios Tzimpragos, Yu Tao, Joseph McMahan, Deeksha Dangwal, Nestan Tsiskaridze, George Michelogiannakis, Dilip P. Vasudevan, Timothy Sherwood
2020	J	`jnl`	PINE: Photonic Integrated Networked Energy efficient datacenters (ENLITENED Program) [Invited]. JOCN Madeleine Glick, Nathan C. Abrams, Qixiang Cheng, Min Yee Teh, Yu-Han Hung, Oscar A. Jimenez, Songtao Liu, Yoshitomo Okawachi, Xiang Meng, Leif Johansson, Manya Ghobadi, Larry Dennison, George Michelogiannakis, John Shalf, Alan Y. Liu, John E. Bowers, Alexander L. Gaeta, Michal Lipson, Keren Bergman
2020	A	`conf`	TAGO: rethinking routing design in high performance reconfigurable networks. SC Min Yee Teh, Yu-Han Hung, George Michelogiannakis, Shijia Yan, Madeleine Glick, John Shalf, Keren Bergman
2020	J	`jnl`	TIGER: Topology-aware Assignment using Ising machines Application to Classical Algorithm Tasks and Quantum Circuit Gates. CoRR Anastasiia Butko, Ilyas Turimbetov, George Michelogiannakis, David Donofrio, Didem Unat, John Shalf
2020	—	`conf`	Understanding Quantum Control Processor Capabilities and Limitations through Circuit Characterization. ICRC Anastasiia Butko, George Michelogiannakis, Samuel Williams, Costin Iancu, David Donofrio, John Shalf, Jonathan Carter, Irfan Siddiqi
2019	—	`conf`	3D photonics as enabling technology for deep 3D DRAM stacking. MEMSYS Sebastian Werner, Pouya Fotouhi, Xian Xiao, Marjan Fariborz, S. J. Ben Yoo, George Michelogiannakis, Dilip P. Vasudevan
2019	A	`conf`	Bandwidth steering in HPC using silicon nanophotonics. SC George Michelogiannakis, Yiwen Shen, Min Yee Teh, Xiang Meng, Benjamin Aivazi, Taylor L. Groves, John Shalf, Madeleine Glick, Manya Ghobadi, Larry Dennison, Keren Bergman
2019	—	`conf`	Extending classical processors to support future large scale quantum accelerators. CF Anastasiia Butko, George Michelogiannakis, David Donofrio, John Shalf
2019	B	`conf`	PARADISE - Post-Moore Architecture and Accelerator Design Space Exploration Using Device Level Simulation and Experiments. ISPASS Dilip P. Vasudevan, George Michelogiannakis, David Donofrio, John Shalf
2019	C	`conf`	SpecLock: Speculative Lock Forwarding. ICCD Pooria M. Yaghini, George Michelogiannakis, Paul V. Gratz
2019	—	`conf`	TIGER: topology-aware task assignment approach using ising machines. CF Anastasiia Butko, George Michelogiannakis, David Donofrio, John Shalf
2018	Misc	`conf`	Architectural Opportunities and Challenges from Emerging Photonics in Future Systems. PSC George Michelogiannakis, Benjamin Aivazi, Yiwen Shen, Larry Dennison, John Shalf, Keren Bergman, Madeleine Glick
2018	C	`conf`	The Pitfalls of Provisioning Exascale Networks: A Trace Replay Analysis for Understanding Communication Performance. ISC Joseph P. Kenny, Khachik Sargsyan, Samuel Knight, George Michelogiannakis, Jeremiah J. Wilke
2017	B	`conf`	APHiD: Hierarchical Task Placement to Enable a Tapered Fat Tree Topology for Lower Power and Cost in HPC Networks. CCGrid George Michelogiannakis, Khaled Z. Ibrahim, John Shalf, Jeremiah J. Wilke, Samuel Knight, Joseph P. Kenny
2017	—	`conf`	CASPER - Configurable design space exploration of programmable architectures for machine learning using beyond moore devices. NANOARCH Dilip P. Vasudevan, George Michelogiannakis, David Donofrio, John Shalf
2017	Misc	`conf`	Last Level Collective Hardware Prefetching For Data-Parallel Applications. HiPC George Michelogiannakis, John Shalf
2017	—	`conf`	Towards an Integrated Strategy to Preserve Digital Computing Performance Scaling Using Emerging Technologies. ISC Workshops Dilip P. Vasudevan, Anastasiia Butko, George Michelogiannakis, David Donofrio, John Shalf
2016	B	`conf`	OpenSoC Fabric: On-chip network generator. ISPASS Farzad Fatollahi-Fard, David Donofrio, George Michelogiannakis, John Shalf
2016	C	`conf`	TiDA: High-Level Programming Abstractions for Data Locality Management. ISC Didem Unat, Tan Nguyen, Weiqun Zhang, Muhammed Nufail Farooqi, Burak Bastem, George Michelogiannakis, Ann S. Almgren, John Shalf
2015	J	`jnl`	Extending Summation Precision for Network Reduction Operations. Int. J. Parallel Program. George Michelogiannakis, Xiaoye S. Li, David H. Bailey, John Shalf
2014	A	`conf`	Collective memory transfers for multi-core chips. ICS George Michelogiannakis, Alexander Williams, Samuel Williams, John Shalf
2014	—	`conf`	OpenSoC Fabric: On-Chip Network Generator: Using Chisel to Generate a Parameterizable On-Chip Interconnect Fabric. NoCArc@MICRO Farzad Fatollahi-Fard, David Donofrio, George Michelogiannakis, John Shalf
2014	—	`conf`	Variable-width datapath for on-chip network static power reduction. NOCS George Michelogiannakis, John Shalf
2013	B	`conf`	A detailed and flexible cycle-accurate Network-on-Chip simulator. ISPASS Nan Jiang, Daniel U. Becker, George Michelogiannakis, James D. Balfour, Brian Towles, David E. Shaw, John Kim, William J. Dally
2013	A	`conf`	Channel reservation protocol for over-subscribed channels and destinations. SC George Michelogiannakis, Nan Jiang, Daniel Becker, William J. Dally
2013	J	`jnl`	Elastic Buffer Flow Control for On-Chip Networks. IEEE Trans. Computers George Michelogiannakis, William J. Dally
2013	C	`conf`	Extending Summation Precision for Network Reduction Operations. SBAC-PAD George Michelogiannakis, Xiaoye S. Li, David H. Bailey, John Shalf
2012	C	`conf`	Adaptive Backpressure: Efficient buffer management for on-chip networks. ICCD Daniel U. Becker, Nan Jiang, George Michelogiannakis, William J. Dally
2012	A*	`conf`	Network congestion avoidance through Speculative Reservation. HPCA Nan Jiang, Daniel U. Becker, George Michelogiannakis, William J. Dally
2011	J	`jnl`	Evaluating Elastic Buffer and Wormhole Flow Control. IEEE Trans. Computers George Michelogiannakis, Daniel Becker, William J. Dally
2011	J	`jnl`	Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks. IEEE Comput. Archit. Lett. George Michelogiannakis, Nan Jiang, Daniel Becker, William J. Dally
2011	A*	`conf`	Packet chaining: efficient single-cycle allocation for on-chip networks. MICRO George Michelogiannakis, Nan Jiang, Daniel Becker, William J. Dally
2010	J	`jnl`	An analysis of on-chip interconnection networks for large-scale chip multiprocessors. ACM Trans. Archit. Code Optim. Daniel Sánchez, George Michelogiannakis, Christos Kozyrakis
2010	—	`conf`	Evaluating Bufferless Flow Control for On-chip Networks. NOCS George Michelogiannakis, Daniel Sánchez, William J. Dally, Christos Kozyrakis
2009	A*	`conf`	Elastic-buffer flow control for on-chip networks. HPCA George Michelogiannakis, James D. Balfour, William J. Dally
2009	A	`conf`	Router designs for elastic buffer on-chip networks. SC George Michelogiannakis, William J. Dally
2007	—	`conf`	Approaching Ideal NoC Latency with Pre-Configured Routes. NOCS George Michelogiannakis, Dionisios N. Pnevmatikatos, Manolis Katevenis