George Gristede

17 papers A 6Journal 4Unranked 7
YearRankTypeTitle / Venue / Authors
2020 — conf
A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference.
VLSI Circuits
Jinwook Oh, Sae Kyu Lee, Mingu Kang, Matthew M. Ziegler, Joel Silberman, Ankur Agrawal, Swagath Venkataramani, Bruce M. Fleischer, Michael Guillorn, Jungwook Choi, Wei Wang, Silvia M. Mueller, Shimon Ben-Yehuda, James Bonanno, Nianzheng Cao, Robert Casatuta, Chia-Yu Chen, Matt Cohen, Ophir Erez, Thomas W. Fox, George Gristede, Howard Haynie, Vicktoria Ivanov, Siyu Koswatta, Shih-Hsien Lo, Martin Lutz, Gary W. Maier, Alex Mesh, Yevgeny Nustov, Scot Rider, Marcel Schaal, Michael Scheuermann, Xiao Sun, Naigang Wang, Fanchieh Yee, Ching Zhou, Vinay Shah, Brian W. Curran, Vijayalakshmi Srinivasan, Pong-Fei Lu, Sunil Shukla, Kailash Gopalakrishnan, Leland Chang
2020 J jnl
Efficient AI System Design With Cross-Layer Approximate Computing.
Proc. IEEE
Swagath Venkataramani, Xiao Sun, Naigang Wang, Chia-Yu Chen, Jungwook Choi, Mingu Kang, Ankur Agarwal, Jinwook Oh, Shubham Jain, Tina Babinsky, Nianzheng Cao, Thomas W. Fox, Bruce M. Fleischer, George Gristede, Michael Guillorn, Howard Haynie, Hiroshi Inoue, Kazuaki Ishizaki, Michael J. Klaiber, Shih-Hsien Lo, Gary W. Maier, Silvia M. Mueller, Michael Scheuermann, Eri Ogawa, Marcel Schaal, Mauricio J. Serrano, Joel Silberman, Christos Vezyrtzis, Wei Wang, Fanchieh Yee, Jintao Zhang, Matthew M. Ziegler, Ching Zhou, Moriyoshi Ohara, Pong-Fei Lu, Brian W. Curran, Sunil Shukla, Vijayalakshmi Srinivasan, Leland Chang, Kailash Gopalakrishnan
2018 — conf
A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference.
VLSI Circuits
Bruce M. Fleischer, Sunil Shukla, Matthew M. Ziegler, Joel Silberman, Jinwook Oh, Vijayalakshmi Srinivasan, Jungwook Choi, Silvia M. Mueller, Ankur Agrawal, Tina Babinsky, Nianzheng Cao, Chia-Yu Chen, Pierce Chuang, Thomas W. Fox, George Gristede, Michael Guillorn, Howard Haynie, Michael J. Klaiber, Dongsoo Lee, Shih-Hsien Lo, Gary W. Maier, Michael Scheuermann, Swagath Venkataramani, Christos Vezyrtzis, Naigang Wang, Fanchieh Yee, Ching Zhou, Pong-Fei Lu, Brian W. Curran, Leland Chang, Kailash Gopalakrishnan
2018 A conf
Across the Stack Opportunities for Deep Learning Acceleration.
ISLPED
Vijayalakshmi Srinivasan, Bruce M. Fleischer, Sunil Shukla, Matthew M. Ziegler, Joel Silberman, Jinwook Oh, Jungwook Choi, Silvia M. Mueller, Ankur Agrawal, Tina Babinsky, Nianzheng Cao, Chia-Yu Chen, Pierce Chuang, Thomas W. Fox, George Gristede, Michael Guillorn, Howard Haynie, Michael J. Klaiber, Dongsoo Lee, Shih-Hsien Lo, Gary W. Maier, Michael Scheuermann, Swagath Venkataramani, Christos Vezyrtzis, Naigang Wang, Fanchieh Yee, Ching Zhou, Pong-Fei Lu, Brian W. Curran, Leland Chang, Kailash Gopalakrishnan
2016 — conf
A Scalable Black-Box Optimization System for Auto-Tuning VLSI Synthesis Programs.
RES4ANT@DATE
Matthew M. Ziegler, Hung-Yi Liu, George Gristede, Bruce Owens, Ricardo Nigaglioni, Luca P. Carloni
2016 A conf
A synthesis-parameter tuning system for autonomous design-space exploration.
DATE
Matthew M. Ziegler, Hung-Yi Liu, George Gristede, Bruce Owens, Ricardo Nigaglioni, Luca P. Carloni
2014 — conf
POWER8 design methodology innovations for improving productivity and reducing power.
CICC
Matthew M. Ziegler, Ruchir Puri, Bob Philhower, Robert L. Franch, Wing K. Luk, Jens Leenstra, Peter Verwegen, Niels Fricke, George Gristede, Eric Fluhr, Victor V. Zyuban
2013 A conf
Power reduction by aggressive synthesis design space exploration.
ISLPED
Matthew M. Ziegler, George Gristede, Victor V. Zyuban
2009 — conf
A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR).
PATMOS
Milena Vratonjic, Matthew M. Ziegler, George Gristede, Victor V. Zyuban, Thomas Mitchell, Ee Cho, Chandu Visweswariah, Vojin G. Oklobdzija
2009 A conf
The opportunity cost of low power design: a case study in circuit tuning.
ISLPED
Matthew M. Ziegler, Victor V. Zyuban, George Gristede, Milena Vratonjic, Joshua Friedrich
2005 J jnl
Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies.
Integr.
Phillip Chin, Charles A. Zukowski, George Gristede, Stephen V. Kosonocky
2004 — conf
Characterization of logic circuit techniques for high leakage CMOS technologies.
ACM Great Lakes Symposium on VLSI
Phillip Chin, Charles A. Zukowski, George Gristede, Stephen V. Kosonocky
2003 J jnl
Low-power circuits and technology for wireless digital systems.
IBM J. Res. Dev.
Stephen V. Kosonocky, Azeez J. Bhavnagarwala, Kenneth Chin, George Gristede, Anne-Marie Haen, Wei Hwang, Mark B. Ketchen, Suhwan Kim, Daniel R. Knebel, Kevin W. Warren, Victor V. Zyuban
2001 A conf
Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design.
ISLPED
W. Chen, Wei Hwang, Prabhakar Kudva, George Gristede, Stephen V. Kosonocky, Rajiv V. Joshi
2000 — conf
A comparison of dual-rail pass transistor logic families in 1.5V, 0.18µm CMOS technology for low power applications.
ACM Great Lakes Symposium on VLSI
George Gristede, Wei Hwang
2000 J jnl
A scannable pulse-to-static conversion register array for self-timed circuits.
IEEE J. Solid State Circuits
Wei Hwang, Rajiv V. Joshi, George Gristede
1990 A conf
Measuring Error Propagation in Waveform Relaxation Algorithms.
ICCAD
Charles A. Zukowski, George Gristede, Albert E. Ruehli