George Economakos

85 papers A 5B 1C 11Misc 1Journal 12Unranked 55

Year	Rank	Type	Title / Venue / Authors
2016	J	`jnl`	A Framework for Interconnection-Aware Domain-Specific Many-Accelerator Synthesis. ACM Trans. Embed. Comput. Syst. Efstathios Sotiriou-Xanthopoulos, Sotirios Xydis, Kostas Siozios, George Economakos, Dimitrios Soudris
2016	J	`jnl`	An Integrated Exploration and Virtual Platform Framework for Many-Accelerator Heterogeneous Systems. ACM Trans. Embed. Comput. Syst. Efstathios Sotiriou-Xanthopoulos, Sotirios Xydis, Kostas Siozios, George Economakos, Dimitrios Soudris
2016	—	`conf`	An OpenCL-based framework for rapid virtual prototyping of heterogeneous architectures. SAMOS Efstathios Sotiriou-Xanthopoulos, Leonard Masing, Kostas Siozios, George Economakos, Dimitrios Soudris, Jürgen Becker
2015	—	`conf`	A power estimation technique for cycle-accurate higher-abstraction SystemC-based CPU models. SAMOS Efstathios Sotiriou-Xanthopoulos, Shalina Percy Delicia, Peter Figuli, Kostas Siozios, George Economakos, Jürgen Becker
2015	—	`conf`	A virtual platform for exploring hierarchical interconnection for many-accelerator systems. SAMOS Efstathios Sotiriou-Xanthopoulos, Sotirios Xydis, Kostas Siozios, George Economakos
2015	—	`conf`	Comparison of OpenCL based design for a medical device on heterogeneous architectures with CPU, GPU and FPGA. Panhellenic Conference on Informatics Efthymia Kazakou, George Economakos
2015	—	`conf`	Evaluation of High-Level Synthesis Techniques for Memory and Datapath Tradeoffs in FPGA Based SoC Architectures. ARC Efstathios Sotiriou-Xanthopoulos, Dionysios Diamantopoulos, George Economakos
2015	—	`conf`	Performance improvements in a modern hardware design environment for control applications. ICIT Christoforos E. Economakos, Maria P. Tzamtzi, Michael G. Skarpetis, George Economakos
2015	B	`conf`	Rapid prototyping and Design Space Exploration methodologies for many-accelerator systems. FPL Efstathios Sotiriou-Xanthopoulos, Sotirios Xydis, Kostas Siozios, George Economakos, Dimitrios Soudris
2015	—	`conf`	Using advanced FPGA SoC technologies for the design of industrial control applications. IISA Christoforos E. Economakos, George Kiokes, George Economakos
2014	J	`jnl`	A framework for rapid evaluation of heterogeneous 3-D NoC architectures. Microprocess. Microsystems Efstathios Sotiriou-Xanthopoulos, Dionysios Diamantopoulos, Kostas Siozios, George Economakos, Dimitrios Soudris
2014	—	`conf`	A scalable FPGA-based architecture for digital controllers and a corresponding rapid prototyping design methodology. ISIE Christoforos E. Economakos, Maria P. Tzamtzi, George Economakos
2014	—	`conf`	Co-design of many-accelerator heterogeneous systems exploiting virtual platforms. ICSAMOS Efstathios Sotiriou-Xanthopoulos, Sotirios Xydis, Kostas Siozios, George Economakos
2014	—	`conf`	Effective Platform-Level Exploration for Heterogeneous Multicores Exploiting Simulation-Induced Slacks. PARMA-DITAM@HiPEAC Efstathios Sotiriou-Xanthopoulos, Sotirios Xydis, Kostas Siozios, George Economakos, Dimitrios Soudris
2014	—	`conf`	Hardware accelerated rician denoise algorithm for high performance magnetic resonance imaging. MobiHealth Efstathios Sotiriou-Xanthopoulos, Sotirios Xydis, Kostas Siozios, George Economakos, Dimitrios Soudris
2014	J	`jnl`	Plug&Chip: A Framework for Supporting Rapid Prototyping of 3D Hybrid Virtual SoCs. ACM Trans. Embed. Comput. Syst. Dionysios Diamantopoulos, Efstathios Sotiriou-Xanthopoulos, Kostas Siozios, George Economakos, Dimitrios Soudris
2014	—	`conf`	Program-based and Model-based PLC Design Environment for Multicore FPGA Architectures. ICINCO (1) Christoforos E. Economakos, Michael G. Skarpetis, George Economakos
2014	J	`jnl`	Systematic Design and Evaluation of Reconfigurable Arithmetic Components in the Deep submicron Domain. J. Circuits Syst. Comput. Dimitris Bekiaris, Sotirios Xydis, George Economakos
2014	—	`conf`	Using high-level synthesis to build memory and datapath optimized DSP accelerators. ICECS Dionysios Diamantopoulos, George Economakos, Dionysios I. Reisis
2013	—	`conf`	A Process-based Reconfigurable SystemC Module for simulation speedup. ICSAMOS Efstathios Sotiriou-Xanthopoulos, Kostas Siozios, George Economakos, Dimitrios Soudris
2013	—	`conf`	A new design paradigm for floating point DSP applications based on ESL/HLS and FPGAs? ISSPIT Dionysios Diamantopoulos, Christoforos E. Economakos, Dimitrios Soudris, George Economakos
2013	C	`conf`	Efficient C level hardware design for floating point biomedical DSP applications. BIBE Harry Sidiropoulos, Efthymia Kazakou, Christoforos E. Economakos, George Economakos
2013	—	`conf`	HVSoCs: A Framework for Rapid Prototyping of 3-D Hybrid Virtual System-on-Chips. IPDPS Workshops Dionysios Diamantopoulos, Kostas Siozios, Efstathios Sotiriou-Xanthopoulos, George Economakos, Dimitrios Soudris
2013	—	`conf`	Rapid prototyping of digital controllers using FPGAs and ESL/HLS design methodologies. ICAC Christoforos E. Economakos, Harry Sidiropoulos, George Economakos
2012	—	`conf`	A Methodology for Efficient Use of OpenCL, ESL and FPGAs in Multi-core Architectures. Euro-Par Workshops Alexandros Bartzas, George Economakos
2012	J	`jnl`	Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs. ACM Trans. Design Autom. Electr. Syst. Sotirios Xydis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos
2012	—	`conf`	ESL as a Gateway from OpenCL to FPGAs: Basic Ideas and Methodology Evaluation. Panhellenic Conference on Informatics George Economakos
2012	C	`conf`	Power Optimization Opportunities for a Reconfigurable Arithmetic Component in the Deep Submicron Domain. DSD Dimitris Bekiaris, George Economakos
2012	—	`conf`	Systematic design and evaluation of a scalable reconfigurable multiplier scheme for HLS environments. ReCoSoC Dimitris Bekiaris, Efstathios Sotiriou-Xanthopoulos, George Economakos, Dimitrios Soudris
2011	—	`conf`	Design and experimentation with low-power morphable multipliers. ICECS Efstathios Sotiriou-Xanthopoulos, Dionysios Diamantopoulos, George Economakos, Dimitrios Soudris
2011	J	`jnl`	High Performance and Area Efficient Flexible DSP Datapath Synthesis. IEEE Trans. Very Large Scale Integr. Syst. Sotirios Xydis, George Economakos, Dimitrios Soudris, Kiamal Z. Pekmestzi
2011	—	`conf`	Low-Power Reconfigurable Component Utilization in a High-Level Synthesis Flow. ReConFig Dimitris Bekiaris, George Economakos, Efstathios Sotiriou-Xanthopoulos, Dimitrios Soudris
2010	—	`conf`	A High Level Synthesis Exploration Framework with Iterative Design Space Partitioning. ISVLSI (Selected papers) Sotirios Xydis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos
2010	—	`conf`	A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis Framework. PATMOS Dimitris Bekiaris, Antonis Papanikolaou, Christos Papameletis, Dimitrios Soudris, George Economakos, Kiamal Z. Pekmestzi
2010	—	`conf`	BIT-width exploration over 3D architectures using high-level synthesis. ICECS Ioannis Koutras, Antonis Papanikolaou, George Economakos, Dimitrios Soudris
2010	A	`conf`	Construction of dual mode components for reconfiguration aware high-level synthesis. DATE George Economakos, Sotirios Xydis, Ioannis Koutras, Dimitrios Soudris
2010	C	`conf`	Designing efficient DSP datapaths through compiler-in-the-loop exploration methodology. ISCAS Sotirios Xydis, Christos Skouroumounis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos
2010	—	`conf`	Efficient High Level Synthesis Exploration Methodology Combining Exhaustive and Gradient-Based Pruned Searching. ISVLSI Sotirios Xydis, Christos Skouroumounis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos
2010	—	`conf`	High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures. ISVLSI Sotirios Xydis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos
2010	—	`conf`	Systematic Exploration of Energy-Efficient Application-Specific Network-on-Chip Architectures. ISVLSI Iasonas Filippopoulos, Iraklis Anagnostopoulos, Alexandros Bartzas, Dimitrios Soudris, George Economakos
2009	—	`conf`	A design methodology for high-performance and low-leakage fixed-point transpose FIR filters. ICECS Dimitris Bekiaris, Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi
2009	—	`conf`	Architectural exploration in biomedical hardware design using a novel behavioral synthesis methodology. EUSIPCO George Economakos
2009	J	`jnl`	Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths. Integr. Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi
2009	J	`jnl`	Extending an embedded RISC microprocessor for efficient translation based Java execution. Microprocess. Microsystems Isidoros Sideris, Kiamal Z. Pekmestzi, George Economakos
2009	—	`conf`	Flexible Datapath Synthesis through Arithmetically Optimized Operation Chaining. AHS Sotirios Xydis, Ioannis Triantafyllou, George Economakos, Kiamal Z. Pekmestzi
2009	A	`conf`	High-level synthesis with coarse grain reconfigurable components. IPDPS George Economakos, Sotirios Xydis
2009	C	`conf`	Optimized Reconfigurable RTL Components for Performance Improvements During High-Level Synthesis. DSD George Economakos, Sotirios Xydis
2009	C	`conf`	Recursive Systematic Convolutional Code Simulation for Ofdm - 802.11p System and FPGA Implementation Using an ESL Methodology. DSD George Kiokes, George Economakos, Angelos Amditis, Nikolaos K. Uzunoglu
2009	—	`conf`	Three dimensional FPGA architectures: A shift paradigm for energy-performance efficient DSP implementations. DPS Kostas Siozios, Dimitrios Soudris, George Economakos
2008	C	`conf`	A Scheduling Postprocessor to Exploit Morphable RTL Components During High-Level Synthesis. DSD George Economakos, Sotirios Xydis
2008	—	`conf`	A flexible architecture for DSP applications combining high performance arithmetic with small scale configurability. EUSIPCO Sotirios Xydis, Isidoros Sideris, George Economakos, Kiamal Z. Pekmestzi
2008	J	`jnl`	A predecoding technique for ILP exploitation in Java processors. J. Syst. Archit. Isidoros Sideris, Kiamal Z. Pekmestzi, George Economakos
2008	—	`conf`	An instruction set extension for java bytecodes translation acceleration. ICSAMOS Isidoros Sideris, Kiamal Z. Pekmestzi, George Economakos
2008	C	`conf`	Efficient implementation of biomedical hardware using open source descriptions and behavioral synthesis. BIBE George Economakos
2008	—	`conf`	Efficient serial and parallel implementation of programmable fir filters based on the merging technique. EUSIPCO Dimitris Bekiaris, George Economakos, Kiamal Z. Pekmestzi
2008	—	`conf`	Mapping DSP Applications onto High-Performance Architectural Templates with Inlined Flexibility. AHS Sotirios Xydis, George Economakos, Dimitrios Soudris, Kiamal Z. Pekmestzi
2008	C	`conf`	Optimized FPGA implementations of demanding PLC programs based on hardware high-level synthesis. ETFA Christoforos E. Economakos, George Economakos
2007	—	`conf`	A Reconfigurable Arithmetic Data-path Based On Regular Interconnection. AHS Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi
2007	—	`conf`	A regular interconnection scheme for efficient mapping of DSP kernels into reconfigurable hardware. EUSIPCO Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi
2007	—	`conf`	Building embedded DSP applications in a Java modeling framework. EUSIPCO Isidoros Sideris, Dimitris Pilitsos, George Economakos, Kiamal Z. Pekmestzi
2007	—	`conf`	Flexibility Inlining into Arithmetic Data-paths Exploiting A Regular Interconnection Scheme. ICSAMOS Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi
2007	—	`conf`	High-level synthesis heuristics for run-time reconfigurable architectures. EUSIPCO George Economakos, Sotirios Xydis
2007	—	`conf`	Power-Efficient and Low Latency Implementation of Programmable FIR filters Using Carry-Save Arithmetic. ICECS Dimitris Bekiaris, Isidoros Sideris, George Economakos, Kiamal Z. Pekmestzi
2007	—	`conf`	Run-time reconfigurable solutions for adaptive control applications. ICINCO-SPSMC George Economakos, Christoforos E. Economakos, Sotirios Xydis
2006	—	`conf`	A Methodology for Design Space Exploration in Embedded DSP Applications. ICECS George Economakos, Kostas Anagnostopoulos, Isidoros Sideris
2006	—	`conf`	A cache based stack folding technique for high performance Java processors. JTRES Isidoros Sideris, George Economakos, Kiamal Z. Pekmestzi
2006	C	`conf`	Behavioral synthesis with SystemC and PSL assertions for interface specification. ISCAS George Economakos
2006	C	`conf`	Bit level architectural exploration technique for the design of low power multipliers. ISCAS George Economakos, Kostas Anagnostopoulos
2006	A	`conf`	High-level synthesis with reconfigurable datapath components. IPDPS George Economakos
2005	—	`conf`	Lowpower design of multipliers using a full-adder isolation technique. ICECS Konstantinos Anagnostopoulos, George Economakos
2002	J	`jnl`	Handling advanced scheduling heuristics under a hardware compiler generation environment. Knowl. Based Syst. George Economakos, Petros Oikonomakos, Ioannis Poulakis, George K. Papakonstantinou, Stamatis Georgoulis
2001	C	`conf`	A Multi-Lingual Synthesis and Verification Environment. DSD George Economakos, Stergios Stergiou, George K. Papakonstantinou, Vassilios Zoukos
2001	A	`conf`	Behavioral synthesis with systemC. DATE George Economakos, Petros Oikonomakos, Ioannis Panagopoulos, Ioannis Poulakis, George K. Papakonstantinou
2000	—	`conf`	A complete specification and implementation methodology for high-level hardware transformations. ICECS George Economakos, Ioannis Drositis, George K. Papakonstantinou
2000	—	`conf`	A top-down interactive behavioral synthesis environment. ICECS Ioannis Poulakis, Petros Economakos, George Economakos, Ioannis Panagopoulos, George K. Papakonstantinou
1999	—	`conf`	A formal method for hardware design using attribute grammars. ICECS George Economakos, George K. Papakonstantinou
1999	—	`conf`	Language Based Design Verification with Semantic Analysis. EUROMICRO George Economakos, George K. Papakonstantinou
1999	—	`conf`	Refinement and Property Checking in High-Level Synthesis using Attribute Grammars. CHARME George Economakos, George K. Papakonstantinou
1998	A	`conf`	AGENDA: An Attribute Grammar Driven Environment for the Design Automation of Digital Systems. DATE George Economakos, George K. Papakonstantinou, Panayotis Tsanakas
1998	—	`conf`	Behavioral synthesis of digital filters using attribute grammars. EUSIPCO George Economakos, George K. Papakonstantinou, Panayiotis Tsanakas
1998	—	`conf`	Exploiting the Use of VHDL Specifications in the AGENDA High-Level Synthesis Environment. EUROMICRO George Economakos, George K. Papakonstantinou
1998	Misc	`conf`	Incorporating multi-pass attribute grammars for the high-level synthesis of ASICs. SAC George Economakos, George K. Papakonstantinou, Panayotis Tsanakas
1997	—	`conf`	Automatic Hardware Synthesis of Nested Loops Using UET Grids and VHDL. HPCN Europe Nectarios Koziris, Theodore Andronikos, George Economakos, George K. Papakonstantinou, Panayotis Tsanakas
1997	—	`conf`	Hardware compilation using attribute grammars. CHARME George Economakos, George K. Papakonstantinou, Kiamal Z. Pekmestzi, Panayotis Tsanakas
1995	J	`jnl`	An attribute grammar approach to high-level automated hardware synthesis. Inf. Softw. Technol. George Economakos, George K. Papakonstantinou, Panayotis Tsanakas