George A. Constantinides

342 papers A* 6A 31B 47C 12Misc 39Journal 129Unranked 76

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Bit-Serial Acceleration of LLM Inference With Mixture-of-Datatype Quantization. IEEE Trans. Computers Yuzong Chen, Chi-Chih Chang, Xilai Dai, Ahmed F. AbouElhamayed, Marta Andronic, George A. Constantinides, Mohamed S. Abdelfattah
2025	J	`jnl`	A3 : an Analytical Low-Rank Approximation Framework for Attention. CoRR Jeffrey T. H. Wong, Cheng Zhang, Xinye Cao, Pedro Gimenes, George A. Constantinides, Wayne Luk, Yiren Zhao
2025	—	`conf`	AMPLE: Event-Driven Accelerator for Mixed-Precision Inference of Graph Neural Networks. EuroMLSys Pedro Gimenes, Aaron Zhao, George A. Constantinides
2025	J	`jnl`	AMPLE: Event-Driven Accelerator for Mixed-Precision Inference of Graph Neural Networks. CoRR Pedro Gimenes, Yiren Zhao, George A. Constantinides
2025	J	`jnl`	An Improved Template for Approximate Computing. CoRR Morteza Rezaalipour, Francesco Costa, Marco Biasion, Rodrigo Otoni, George A. Constantinides, Laura Pozzi
2025	Misc	`conf`	Banked Memories for Soft SIMT Processors. FCCM Martin Langhammer, George A. Constantinides
2025	J	`jnl`	Banked Memories for Soft SIMT Processors. CoRR Martin Langhammer, George A. Constantinides
2025	A*	`conf`	BitMoD: Bit-serial Mixture-of-Datatype LLM Acceleration. HPCA Yuzong Chen, Ahmed F. AbouElhamayed, Xilai Dai, Yang Wang, Marta Andronic, George A. Constantinides, Mohamed S. Abdelfattah
2025	J	`jnl`	Constraint-Aware E-Graph Rewriting for Hardware Performance Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Samuel Coward, Theo Drane, George A. Constantinides
2025	A	`conf`	Greater than the Sum of its LUTs: Scaling Up LUT-based Neural Networks with AmigoLUT. FPGA Olivia Weng, Marta Andronic, Danial Zuberi, Jiaqing Chen, Caleb Geniesse, George A. Constantinides, Nhan Tran, Nicholas J. Fraser, Javier Mauricio Duarte, Ryan Kastner
2025	Misc	`conf`	NeuraLUT-Assemble: Hardware-Aware Assembling of Sub-Neural Networks for Efficient LUT Inference. FCCM Marta Andronic, George A. Constantinides
2025	J	`jnl`	NeuraLUT-Assemble: Hardware-aware Assembling of Sub-Neural Networks for Efficient LUT Inference. CoRR Marta Andronic, George A. Constantinides
2025	—	`conf`	Permuting Accumulation Order for Low-Precision Machine Learning. ASAP Ebby Samson, Tony Liu, Wayne Luk, George A. Constantinides
2025	Misc	`conf`	Ph.D. Project Hardware-Aware Neural Networks. FCCM Marta Andronic, George A. Constantinides
2025	J	`jnl`	PolyLUT: Ultra-Low Latency Polynomial Inference With Hardware-Aware Structured Pruning. IEEE Trans. Computers Marta Andronic, Jiawen Li, George A. Constantinides
2025	J	`jnl`	PolyLUT: Ultra-low Latency Polynomial Inference with Hardware-Aware Structured Pruning. CoRR Marta Andronic, Jiawen Li, George A. Constantinides
2025	A	`conf`	ReducedLUT: Table Decomposition with "Don't Care" Conditions. FPGA Oliver Cassidy, Marta Andronic, Samuel Coward, George A. Constantinides
2025	J	`jnl`	Training with Fewer Bits: Unlocking Edge LLMs Training with Stochastic Rounding. CoRR Taowen Liu, Marta Andronic, Deniz Gündüz, George A. Constantinides
2025	J	`jnl`	hls4ml: A Flexible, Open-Source Platform for Deep Learning Acceleration on Reconfigurable Hardware. CoRR Jan-Frederik Schulte, Benjamin Ramhorst, Chang Sun, Jovan Mitrevski, Nicolò Ghielmetti, Enrico Lupi, Dimitrios Danopoulos, Vladimir Loncar, Javier M. Duarte, David Burnette, Lauri Laatu, Stylianos Tzelepis, Konstantinos Axiotis, Quentin Berthet, Haoyan Wang, Paul White, Suleyman Demirsoy, Marco Colombo, Thea Aarrestad, Sioni Summers, Maurizio Pierini, Giuseppe Di Guglielmo, Jennifer Ngadiuba, Javier Campos, Benjamin Hawks, Abhijith Gandrakota, Farah Fahim, Nhan Tran, George A. Constantinides, Zhiqiang Que, Wayne Luk, Alexander D. Tapper, Duc Hoang, Noah Paladino, Philip C. Harris, Bo-Cheng Lai, Manuel Blanco Valentin, Ryan F. Forelli, Seda Ogrenci, Lino Gerlach, Rian Flynn, Mia Liu, Daniel Diaz, Elham E Khoda, Melissa Quinnan, Russell Solares, Santosh Parajuli, Mark S. Neubauer, Christian Herwig, Ho Fung Tsoi, Dylan S. Rankin, Shih-Chieh Hsu, Scott Hauck
2024	A	`conf`	A Statically and Dynamically Scalable Soft GPGPU. FPGA Martin Langhammer, George A. Constantinides
2024	J	`jnl`	A Statically and Dynamically Scalable Soft GPGPU. CoRR Martin Langhammer, George A. Constantinides
2024	—	`conf`	Automated Feature Testing of Verilog Parsers using Fuzzing (Registered Report). FUZZING Quentin Corradi, John Wickerson, George A. Constantinides
2024	J	`jnl`	BitMoD: Bit-serial Mixture-of-Datatype LLM Acceleration. CoRR Yuzong Chen, Ahmed F. AbouElhamayed, Xilai Dai, Yang Wang, Marta Andronic, George A. Constantinides, Mohamed S. Abdelfattah
2024	C	`conf`	Combining Power and Arithmetic Optimization via Datapath Rewriting. ARITH Samuel Coward, Theo Drane, Emiliano Morini, George A. Constantinides
2024	J	`jnl`	Combining Power and Arithmetic Optimization via Datapath Rewriting. CoRR Samuel Coward, Theo Drane, Emiliano Morini, George A. Constantinides
2024	B	`conf`	Exploring FPGA designs for MX and beyond. FPL Ebby Samson, Naveen Mellempudi, Wayne Luk, George A. Constantinides
2024	J	`jnl`	Exploring FPGA designs for MX and beyond. CoRR Ebby Samson, Naveen Mellempudi, Wayne Luk, George A. Constantinides
2024	J	`jnl`	LQER: Low-Rank Quantization Error Reconstruction for LLMs. CoRR Cheng Zhang, Jianyi Cheng, George A. Constantinides, Yiren Zhao
2024	B	`conf`	NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions. FPL Marta Andronic, George A. Constantinides
2024	J	`jnl`	NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions. CoRR Marta Andronic, George A. Constantinides
2024	J	`jnl`	Optimised Grouped-Query Attention Mechanism for Transformers. CoRR Yuang Chen, Cheng Zhang, Xitong Gao, Robert D. Mullins, George A. Constantinides, Yiren Zhao
2024	J	`jnl`	QERA: an Analytical Framework for Quantization Error Reconstruction. CoRR Cheng Zhang, Jeffrey T. H. Wong, Can Xiao, George A. Constantinides, Yiren Zhao
2024	J	`jnl`	ROVER: RTL Optimization via Verified E-Graph Rewriting. CoRR Samuel Coward, Theo Drane, George A. Constantinides
2024	J	`jnl`	ROVER: RTL Optimization via Verified E-Graph Rewriting. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Samuel Coward, Theo Drane, George A. Constantinides
2024	J	`jnl`	ReducedLUT: Table Decomposition with "Don't Care" Conditions. CoRR Oliver Cassidy, Marta Andronic, Samuel Coward, George A. Constantinides
2024	—	`conf`	Soft GPGPU versus IP cores: Quantifying and Reducing the Performance Gap. HEART Martin Langhammer, George A. Constantinides
2024	J	`jnl`	Soft GPGPU versus IP cores: Quantifying and Reducing the Performance Gap. CoRR Martin Langhammer, George A. Constantinides
2024	J	`jnl`	Unlocking the Global Synergies in Low-Rank Adapters. CoRR Zixi Zhang, Cheng Zhang, Xitong Gao, Robert D. Mullins, George A. Constantinides, Yiren Zhao
2023	—	`conf`	A Parametrizable Template for Approximate Logic Synthesis. DSN-W Morteza Rezaalipour, Marco Biasion, Ilaria Scarabottolo, George A. Constantinides, Laura Pozzi
2023	Misc	`conf`	ATHEENA: A Toolflow for Hardware Early-Exit Network Automation. FCCM Benjamin Biggs, Christos-Savvas Bouganis, George A. Constantinides
2023	J	`jnl`	ATHEENA: A Toolflow for Hardware Early-Exit Network Automation. CoRR Benjamin Biggs, Christos-Savvas Bouganis, George A. Constantinides
2023	A*	`conf`	Automating Constraint-Aware Datapath Optimization using E-Graphs. DAC Samuel Coward, George A. Constantinides, Theo Drane
2023	J	`jnl`	Automating Constraint-Aware Datapath Optimization using E-Graphs. CoRR Samuel Coward, George A. Constantinides, Theo Drane
2023	J	`jnl`	Balancing Static Islands in Dynamically Scheduled Circuits Using Continuous Petri Nets. IEEE Trans. Computers Jianyi Cheng, Estíbaliz Fraca, John Wickerson, George A. Constantinides
2023	—	`conf`	Combining E-Graphs with Abstract Interpretation. SOAP@PLDI Samuel Coward, George A. Constantinides, Theo Drane
2023	B	`conf`	Datapath Verification via Word-Level E-Graph Rewriting. FMCAD Samuel Coward, Emiliano Morini, Bryan Tan, Theo Drane, George A. Constantinides
2023	J	`jnl`	Datapath Verification via Word-Level E-Graph Rewriting. CoRR Samuel Coward, Emiliano Morini, Bryan Tan, Theo Drane, George A. Constantinides
2023	J	`jnl`	Enabling Binary Neural Network Training on the Edge. ACM Trans. Embed. Comput. Syst. Erwei Wang, James J. Davis, Daniele Moro, Piotr Zielinski, Jia Jie Lim, Claudionor Coelho, Satrajit Chatterjee, Peter Y. K. Cheung, George A. Constantinides
2023	—	`conf`	ErrorEval: an Open-Source Worst-Case-Error Evaluation Framework for Approximate Computing. CF Morteza Rezaalipour, Lorenzo Ferretti, Ilaria Scarabottolo, George A. Constantinides, Laura Pozzi
2023	—	`conf`	FPGA Resource-aware Structured Pruning for Real-Time Neural Networks. ICFPT Benjamin Ramhorst, Vladimir Loncar, George A. Constantinides
2023	J	`jnl`	FPGA Resource-aware Structured Pruning for Real-Time Neural Networks. CoRR Benjamin Ramhorst, George A. Constantinides, Vladimir Loncar
2023	J	`jnl`	Horizon-Independent Preconditioner Design for Linear Predictive Control. IEEE Trans. Autom. Control. Ian McInerney, Eric C. Kerrigan, George A. Constantinides
2023	J	`jnl`	Logic Shrinkage: Learned Connectivity Sparsification for LUT-Based Neural Networks. ACM Trans. Reconfigurable Technol. Syst. Erwei Wang, Marie Auffret, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed S. Abdelfattah, James J. Davis
2023	—	`conf`	Multi-Metric SMT-Based Evaluation of Worst-Case-Error for Approximate Circuits. DSN-W Morteza Rezaalipour, Lorenzo Ferretti, Ilaria Scarabottolo, George A. Constantinides, Laura Pozzi
2023	Misc	`conf`	Multiplier Optimization via E-Graph Rewriting. ACSSC Andy Wanna, Samuel Coward, Theo Drane, George A. Constantinides, Milos D. Ercegovac
2023	J	`jnl`	Multiplier Optimization via E-Graph Rewriting. CoRR Andy Wanna, Samuel Coward, Theo Drane, George A. Constantinides, Milos D. Ercegovac
2023	J	`jnl`	Parallelising Control Flow in Dynamic-scheduling High-level Synthesis. ACM Trans. Reconfigurable Technol. Syst. Jianyi Cheng, Lana Josipovic, John Wickerson, George A. Constantinides
2023	—	`conf`	PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inference. ICFPT Marta Andronic, George A. Constantinides
2023	J	`jnl`	PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inference. CoRR Marta Andronic, George A. Constantinides
2023	A*	`conf`	Revisiting Block-based Quantisation: What is Important for Sub-8-bit LLM Inference? EMNLP Cheng Zhang, Jianyi Cheng, Ilia Shumailov, George A. Constantinides, Yiren Zhao
2023	J	`jnl`	Revisiting Block-based Quantisation: What is Important for Sub-8-bit LLM Inference? CoRR Cheng Zhang, Jianyi Cheng, Ilia Shumailov, George A. Constantinides, Yiren Zhao
2023	B	`conf`	eGPU: A 750 MHz Class Soft GPGPU for FPGA. FPL Martin Langhammer, George A. Constantinides
2023	J	`jnl`	eGPU: A 750 MHz Class Soft GPGPU for FPGA. CoRR Martin Langhammer, George A. Constantinides
2022	J	`jnl`	A Case for Precise, Fine-Grained Pointer Synthesis in High-Level Synthesis. ACM Trans. Design Autom. Electr. Syst. Nadesh Ramanathan, George A. Constantinides, John Wickerson
2022	J	`jnl`	A Formal Framework for Maximum Error Estimation in Approximate Logic Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi
2022	J	`jnl`	Abstract Interpretation on E-Graphs. CoRR Samuel Coward, George A. Constantinides, Theo Drane
2022	—	`conf`	Area-Efficient Memory Scheduling for Dynamically Scheduled High-Level Synthesis. FPT Xuefei He, Jianyi Cheng, George A. Constantinides
2022	C	`conf`	Automatic Datapath Optimization using E-Graphs. ARITH Samuel Coward, George A. Constantinides, Theo Drane
2022	J	`jnl`	Automatic Datapath Optimization using E-Graphs. CoRR Samuel Coward, George A. Constantinides, Theo Drane
2022	J	`jnl`	Combining E-Graphs with Abstract Interpretation. CoRR Samuel Coward, George A. Constantinides, Theo Drane
2022	J	`jnl`	DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson
2022	Misc	`conf`	Dynamic C-Slow Pipelining for HLS. FCCM Jianyi Cheng, John Wickerson, George A. Constantinides
2022	B	`conf`	Dynamic Inter-Block Scheduling for HLS. FPL Jianyi Cheng, Lana Josipovic, George A. Constantinides, John Wickerson
2022	J	`jnl`	Efficient Memory Arbitration in High-Level Synthesis From Multi-Threaded Code. IEEE Trans. Computers Jianyi Cheng, Shane T. Fleming, Yu Ting Chen, Jason Helge Anderson, John Wickerson, George A. Constantinides
2022	A	`conf`	Finding and Finessing Static Islands in Dynamically Scheduled Circuits. FPGA Jianyi Cheng, John Wickerson, George A. Constantinides
2022	J	`jnl`	High-level Synthesis using the Julia Language. CoRR Benjamin Biggs, Ian McInerney, Eric C. Kerrigan, George A. Constantinides
2022	A	`conf`	Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference. FPGA Erwei Wang, James J. Davis, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed S. Abdelfattah
2022	—	`conf`	MIDAS: Mutual Information Driven Approximate Synthesis. ISVLSI Sina Boroumand, Christos-Savvas Bouganis, George A. Constantinides
2022	B	`conf`	POLSCA: Polyhedral High-Level Synthesis with Compiler Transformations. FPL Ruizhe Zhao, Jianyi Cheng, Wayne Luk, George A. Constantinides
2021	J	`jnl`	Digit Stability Inference for Iterative Methods Using Redundant Number Representation. IEEE Trans. Computers He Li, Ian McInerney, James J. Davis, George A. Constantinides
2021	—	`conf`	Enabling Binary Neural Network Training on the Edge. EMDL@MobiSys Erwei Wang, James J. Davis, Daniele Moro, Piotr Zielinski, Jia Jie Lim, Claudionor Coelho, Satrajit Chatterjee, Peter Y. K. Cheung, George A. Constantinides
2021	J	`jnl`	Enabling Binary Neural Network Training on the Edge. CoRR Erwei Wang, James J. Davis, Daniele Moro, Piotr Zielinski, Claudionor Coelho, Satrajit Chatterjee, Peter Y. K. Cheung, George A. Constantinides
2021	B	`conf`	Exploiting the Correlation between Dependence Distance and Latency in Loop Pipelining for HLS. FPL Jianyi Cheng, John Wickerson, George A. Constantinides
2021	J	`jnl`	Global Analysis of C Concurrency in High-Level Synthesis. IEEE Trans. Very Large Scale Integr. Syst. Nadesh Ramanathan, George A. Constantinides, John Wickerson
2021	—	`conf`	Learning Boolean Circuits from Examples for Approximate Logic Synthesis. ASP-DAC Sina Boroumand, Christos-Savvas Bouganis, George A. Constantinides
2021	J	`jnl`	Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference. CoRR Erwei Wang, James J. Davis, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed S. Abdelfattah
2021	J	`jnl`	Nonideality-Aware Training for Accurate and Robust Low-Power Memristive Neural Networks. CoRR Dovydas Joksas, Erwei Wang, Nikolaos Barmpatsalos, Wing H. Ng, Anthony J. Kenyon, George A. Constantinides, Adnan Mehonic
2021	A	`conf`	Probabilistic Optimization for High-Level Synthesis. FPGA Jianyi Cheng, John Wickerson, George A. Constantinides
2021	Misc	`conf`	Probabilistic Scheduling in High-Level Synthesis. FCCM Jianyi Cheng, John Wickerson, George A. Constantinides
2021	—	`conf`	Rigorous Roundoff Error Analysis of Probabilistic Floating-Point Computations. CAV (2) George A. Constantinides, Fredrik Dahlqvist, Zvonimir Rakamaric, Rocco Salvia
2021	J	`jnl`	Rigorous Roundoff Error Analysis of Probabilistic Floating-Point Computations. CoRR George A. Constantinides, Fredrik Dahlqvist, Zvonimir Rakamaric, Rocco Salvia
2020	J	`jnl`	Approximate Logic Synthesis: A Survey. Proc. IEEE Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi, Sherief Reda
2020	A	`conf`	Combining Dynamic & Static Scheduling in High-level Synthesis. FPGA Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson
2020	J	`jnl`	Digit Stability Inference for Iterative Methods Using Redundant Number Representation. CoRR He Li, Ian McInerney, James J. Davis, George A. Constantinides
2020	J	`jnl`	Horizon-independent Preconditioner Design for Linear Predictive Control. CoRR Ian McInerney, Eric C. Kerrigan, George A. Constantinides
2020	J	`jnl`	LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference. IEEE Trans. Computers Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides
2020	B	`conf`	Precise Pointer Analysis in High-Level Synthesis. FPL Nadesh Ramanathan, George A. Constantinides, John Wickerson
2020	J	`jnl`	architect: Arbitrary-Precision Hardware With Digit Elision for Efficient Iterative Compute. IEEE Trans. Very Large Scale Integr. Syst. He Li, James J. Davis, John Wickerson, George A. Constantinides
2019	Misc	`conf`	A Probabilistic Approach to Floating-Point Arithmetic. ACSSC Fredrik Dahlqvist, Rocco Salvia, George A. Constantinides
2019	J	`jnl`	A Probabilistic Approach to Floating-Point Arithmetic. CoRR Fredrik Dahlqvist, Rocco Salvia, George A. Constantinides
2019	J	`jnl`	ARCHITECT: Arbitrary-precision Hardware with Digit Elision for Efficient Iterative Compute. CoRR He Li, James J. Davis, John Wickerson, George A. Constantinides
2019	—	`conf`	Accelerated Approximate Nearest Neighbors Search Through Hierarchical Product Quantization. FPT Ameer M. S. Abdelhadi, Christos-Savvas Bouganis, George A. Constantinides
2019	—	`conf`	Automatic Generation of Multi-Precision Multi-Arithmetic CNN Accelerators for FPGAs. FPT Yiren Zhao, Xitong Gao, Xuan Guo, Junyi Liu, Erwei Wang, Robert Mullins, Peter Y. K. Cheung, George A. Constantinides, Cheng-Zhong Xu
2019	J	`jnl`	Automatic Generation of Multi-precision Multi-arithmetic CNN Accelerators for FPGAs. CoRR Yiren Zhao, Xitong Gao, Xuan Guo, Junyi Liu, Erwei Wang, Robert Mullins, Peter Y. K. Cheung, George A. Constantinides, Cheng-Zhong Xu
2019	J	`jnl`	Automatic Software and Computing Hardware Codesign for Predictive Control. IEEE Trans. Control. Syst. Technol. Bulat Khusainov, Eric C. Kerrigan, George A. Constantinides
2019	J	`jnl`	Bounding Computational Complexity under Cost Function Scaling in Predictive Control. CoRR Ian McInerney, Eric C. Kerrigan, George A. Constantinides
2019	J	`jnl`	Calculated Risks: Quantifying Timing Error Probability With Extended Static Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kevin E. Murray, Andrea Suardi, Vaughn Betz, George A. Constantinides
2019	J	`jnl`	Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going. CoRR Erwei Wang, James J. Davis, Ruizhe Zhao, Ho-Cheung Ng, Xinyu Niu, Wayne Luk, Peter Y. K. Cheung, George A. Constantinides
2019	J	`jnl`	Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going. ACM Comput. Surv. Erwei Wang, James J. Davis, Ruizhe Zhao, Ho-Cheung Ng, Xinyu Niu, Wayne Luk, Peter Y. K. Cheung, George A. Constantinides
2019	A	`conf`	EASY: Efficient Arbiter SYnthesis from Multi-threaded Code. FPGA Jianyi Cheng, Shane T. Fleming, Yu Ting Chen, Jason Helge Anderson, George A. Constantinides
2019	Misc	`conf`	Formalizing Loop-Carried Dependencies in Coq for High-Level Synthesis. FCCM Florian Faissole, George A. Constantinides, David B. Thomas
2019	J	`jnl`	LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference. CoRR Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides
2019	Misc	`conf`	LUTNet: Rethinking Inference in FPGA Soft Logic. FCCM Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides
2019	J	`jnl`	LUTNet: Rethinking Inference in FPGA Soft Logic. CoRR Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides
2019	—	`conf`	Modeling Round-off Error in the Fast Gradient Method for Predictive Control. CDC Ian McInerney, Eric C. Kerrigan, George A. Constantinides
2019	A*	`conf`	Partition and Propagate: an Error Derivation Algorithm for the Design of Approximate Circuits. DAC Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi
2019	J	`jnl`	Rethinking Arithmetic for Deep Neural Networks. CoRR George A. Constantinides
2018	C	`conf`	A High Throughput Polynomial and Rational Function Approximations Evaluator. ARITH Nicolas Brisebarre, George A. Constantinides, Milos Ercezovac, Silviu-Ioan Filip, Matei Istoan, Jean-Michel Muller
2018	—	`conf`	An Application- and Platform-agnostic Runtime Management Framework for Multicore Systems. PECCS Graeme M. Bragg, Charles Leech, Domenico Balsamo, James J. Davis, Eduardo Wächter, Geoff V. Merrett, George A. Constantinides, Bashir M. Al-Hashimi
2018	B	`conf`	An Efficient FPGA-based Axis-Aligned Box Tool for Embedded Computer Graphics. FPL Georgios Chatzianastasiou, George A. Constantinides
2018	Misc	`conf`	Concurrency-Aware Thread Scheduling for High-Level Synthesis. FCCM Nadesh Ramanathan, George A. Constantinides, John Wickerson
2018	C	`conf`	Digit Elision for Arbitrary-accuracy Iterative Computation. ARITH He Li, James J. Davis, John Wickerson, George A. Constantinides
2018	—	`conf`	Hardware Compilation of Deep Neural Networks: An Overview. ASAP Ruizhe Zhao, Shuanglong Liu, Ho-Cheung Ng, Erwei Wang, James J. Davis, Xinyu Niu, Xiwei Wang, Huifeng Shi, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2018	J	`jnl`	KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs. ACM Trans. Reconfigurable Technol. Syst. James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides
2018	—	`conf`	KOCL: Kernel-level Power Estimation for Arbitrary FPGA-SoC-accelerated OpenCL Applications. IWOCL James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides
2018	J	`jnl`	Polyhedral-Based Dynamic Loop Pipelining for High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Junyi Liu, John Wickerson, Samuel Bayliss, George A. Constantinides
2018	J	`jnl`	Scheduling Weakly Consistent C Concurrency for Reconfigurable Hardware. IEEE Trans. Computers Nadesh Ramanathan, John Wickerson, George A. Constantinides
2017	J	`jnl`	Automatic Software and Computing Hardware Co-design for Predictive Control. CoRR Bulat Khusainov, Eric C. Kerrigan, George A. Constantinides
2017	A*	`conf`	Automatically comparing memory consistency models. POPL John Wickerson, Mark Batty, Tyler Sorensen, George A. Constantinides
2017	J	`jnl`	Certified Roundoff Error Bounds Using Semidefinite Programming. ACM Trans. Math. Softw. Victor Magron, George A. Constantinides, Alastair F. Donaldson
2017	J	`jnl`	Custom Multicache Architectures for Heap Manipulating Programs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Felix Winterstein, Kermin Elliott Fleming, Hsin-Jung Yang, George A. Constantinides
2017	A	`conf`	FPGAs in the Cloud. FPGA George A. Constantinides
2017	A	`conf`	Hardware Synthesis of Weakly Consistent C Concurrency. FPGA Nadesh Ramanathan, Shane T. Fleming, John Wickerson, George A. Constantinides
2017	J	`jnl`	KOCL: Power Self- Awareness for Arbitrary FPGA-SoC-Accelerated OpenCL Applications. IEEE Des. Test James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides
2017	J	`jnl`	Nonlinear Predictive Control on a Heterogeneous Computing Platform. CoRR Bulat Khusainov, Eric C. Kerrigan, Andrea Suardi, George A. Constantinides
2017	—	`conf`	Pass a pointer: Exploring shared virtual memory abstractions in OpenCL tools for FPGAs. FPT Felix Winterstein, George A. Constantinides
2017	A	`conf`	Quantifying error: Extending static timing analysis with probabilistic transitions. DATE Kevin E. Murray, Andrea Suardi, Vaughn Betz, George A. Constantinides
2017	Misc	`conf`	Run fast when you can: Loop pipelining with uncertain and non-uniform memory dependencies. ACSSC Junyi Liu, John Wickerson, Samuel Bayliss, George A. Constantinides
2017	B	`conf`	STRIPE: Signal selection for runtime power estimation. FPL James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides
2017	B	`conf`	Tile size selection for optimized memory reuse in high-level synthesis. FPL Junyi Liu, John Wickerson, George A. Constantinides
2017	—	`conf`	architect: Arbitrary-precision constant-hardware iterative compute. FPT He Li, James J. Davis, John Wickerson, George A. Constantinides
2016	A	`conf`	A Case for Work-stealing on FPGAs with OpenCL Atomics. FPGA Nadesh Ramanathan, John Wickerson, Felix Winterstein, George A. Constantinides
2016	—	`conf`	An efficient implementation of online arithmetic. FPT Yiren Zhao, John Wickerson, George A. Constantinides
2016	A	`conf`	Automatically Optimizing the Latency, Area, and Accuracy of C Programs for High-Level Synthesis. FPGA Xitong Gao, John Wickerson, George A. Constantinides
2016	Misc	`conf`	Balancing Locality and Concurrency: Solving Sparse Triangular Systems on GPUs. HiPC Andrea Picciau, Gordon E. Inggs, John Wickerson, Eric C. Kerrigan, George A. Constantinides
2016	Misc	`conf`	KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs. FCCM Eddie Hung, James J. Davis, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides
2016	A	`conf`	Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only). FPGA James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides
2016	Misc	`conf`	Loop Splitting for Efficient Pipelining in High-Level Synthesis. FCCM Junyi Liu, John Wickerson, George A. Constantinides
2016	—	`conf`	Multi-objective Co-design for model predictive control with an FPGA. ECC Bulat Khusainov, Eric C. Kerrigan, George A. Constantinides
2016	J	`jnl`	Separation Logic for High-Level Synthesis. ACM Trans. Reconfigurable Technol. Syst. Felix J. Winterstein, Samuel R. Bayliss, George A. Constantinides
2016	—	`conf`	What is different about embedded optimization? ECC Eric C. Kerrigan, Bulat Khusainov, George A. Constantinides
2015	J	`jnl`	A Low Complexity Scaling Method for the Lanczos Kernel in Fixed-Point Arithmetic. IEEE Trans. Computers Juan Luis Jerez, George A. Constantinides, Eric C. Kerrigan
2015	J	`jnl`	Certified Roundoff Error Bounds Using Semidefinite Programming. CoRR Victor Magron, George A. Constantinides, Alastair F. Donaldson
2015	J	`jnl`	Communication Optimization of Iterative Sparse Matrix-Vector Multiply on GPUs and FPGAs. IEEE Trans. Parallel Distributed Syst. Abid Rafique, George A. Constantinides, Nachiket Kapre
2015	—	`conf`	Computer architectures to close the loop in real-time optimization. CDC Eric C. Kerrigan, George A. Constantinides, Andrea Suardi, Andrea Picciau, Bulat Khusainov
2015	—	`conf`	Custom-sized caches in application-specific memory hierarchies. FPT Felix Winterstein, Kermin Fleming, Hsin-Jung Yang, John Wickerson, George A. Constantinides
2015	A	`conf`	Delay-Bounded Routing for Shadow Registers. FPGA Eddie Hung, Joshua M. Levine, Edward A. Stott, George A. Constantinides, Wayne Luk
2015	—	`conf`	Fast FPGA prototyping toolbox for embedded optimization. ECC Andrea Suardi, Eric C. Kerrigan, George A. Constantinides
2015	J	`jnl`	Imprecise Datapath Design: An Overclocking Approach. ACM Trans. Reconfigurable Technol. Syst. Kan Shi, David Boland, George A. Constantinides
2015	A	`conf`	MATCHUP: Memory Abstractions for Heap Manipulating Programs. FPGA Felix Winterstein, Kermin Fleming, Hsin-Jung Yang, Samuel Bayliss, George A. Constantinides
2015	A	`conf`	Numerical Program Optimization for High-Level Synthesis. FPGA Xitong Gao, George A. Constantinides
2015	Misc	`conf`	Offline Synthesis of Online Dependence Testing: Parametric Loop Pipelining for HLS. FCCM Junyi Liu, Samuel Bayliss, George A. Constantinides
2015	A	`ed.`	Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, February 22-24, 2015 FPGA George A. Constantinides, Deming Chen
2015	B	`conf`	PushPush: Seamless integration of hardware and software objects via function calls over AXI. FPL Shane T. Fleming, Ivan Beretta, David B. Thomas, George A. Constantinides, Dan R. Ghica
2015	J	`jnl`	Seeing Shapes in Clouds: On the Performance-Cost trade-off for Heterogeneous Infrastructure-as-a-Service. CoRR Gordon Inggs, David B. Thomas, George A. Constantinides, Wayne Luk
2015	A	`conf`	System-level Linking of Synthesised Hardware and Compiled Software Using a Higher-order Type System. FPGA Shane T. Fleming, David B. Thomas, George A. Constantinides, Dan R. Ghica
2015	A	`conf`	Transparent linking of compiled software and synthesized hardware. DATE David B. Thomas, Shane T. Fleming, George A. Constantinides, Dan R. Ghica
2014	B	`conf`	Area implications of memory partitioning for high-level synthesis on FPGAs. FPL Luca Gallo, Alessandro Cilardo, David B. Thomas, Samuel Bayliss, George A. Constantinides
2014	J	`jnl`	Classification on variation maps: a new placement strategy to alleviate process variation on FPGA. IEICE Electron. Express Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung
2014	Misc	`conf`	Compiling Higher Order Functional Programs to Composable Digital Hardware. FCCM Eduardo Aguilar-Pelaez, Samuel Bayliss, Alex I. Smith, Felix Winterstein, Dan R. Ghica, David B. Thomas, George A. Constantinides
2014	J	`jnl`	Constrained LQR for low-precision data representation. Autom. Stefano Longo, Eric C. Kerrigan, George A. Constantinides
2014	A*	`conf`	Datapath Synthesis for Overclocking: Online Arithmetic for Latency-Accuracy Trade-offs. DAC Kan Shi, David Boland, Edward A. Stott, Samuel Bayliss, George A. Constantinides
2014	—	`conf`	Efficient FPGA implementation of digit parallel online arithmetic operators. FPT Kan Shi, David Boland, George A. Constantinides
2014	J	`jnl`	Embedded Online Optimization for Model Predictive Control at Megahertz Rates. IEEE Trans. Autom. Control. Juan Luis Jerez, Paul J. Goulart, Stefan Richter, George A. Constantinides, Eric C. Kerrigan, Manfred Morari
2014	B	`conf`	FPGA implementation of an interior point method for high-speed model predictive control. FPL Junyi Liu, Helfried Peyrl, Andreas Burg, George A. Constantinides
2014	—	`conf`	GPU vs FPGA: A Comparative Analysis for Non-standard Precision. ARC Umar Ibrahim Minhas, Samuel Bayliss, George A. Constantinides
2014	J	`jnl`	Mitigation of process variation effect in FPGAs with partial rerouting method. IEICE Electron. Express Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung
2014	J	`jnl`	On the Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays. IEEE Trans. Computers Theo A. Drane, Thomas M. Rose, George A. Constantinides
2014	J	`jnl`	Predictive Control Using an FPGA With Application to Aircraft Control. IEEE Trans. Control. Syst. Technol. Edward Nicholas Hartley, Juan Luis Jerez, Andrea Suardi, Jan M. Maciejowski, Eric C. Kerrigan, George A. Constantinides
2014	Misc	`conf`	Separation Logic-Assisted Code Transformations for Efficient High-Level Synthesis. FCCM Felix Winterstein, Samuel Bayliss, George A. Constantinides
2014	A	`ed.`	The 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '14, Monterey, CA, USA - February 26 - 28, 2014 FPGA Vaughn Betz, George A. Constantinides
2013	J	`jnl`	A Scalable Precision Analysis Framework. IEEE Trans. Multim. David Boland, George A. Constantinides
2013	—	`conf`	A predictive control solver for low-precision data representation. ECC Stefano Longo, Eric C. Kerrigan, George A. Constantinides
2013	B	`conf`	A variation-adaptive retiming method exploiting reconfigurability. FPL Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung
2013	Misc	`conf`	Accuracy-Performance Tradeoffs on an FPGA through Overclocking. FCCM Kan Shi, David Boland, George A. Constantinides
2013	Misc	`conf`	Application Composition and Communication Optimization in Iterative Solvers Using FPGAs. FCCM Abid Rafique, Nachiket Kapre, George A. Constantinides
2013	J	`jnl`	Control-Theoretic Forward Error Analysis of Iterative Numerical Algorithms. IEEE Trans. Autom. Control. Ammar Hasan, Eric C. Kerrigan, George A. Constantinides
2013	J	`jnl`	Embedded Online Optimization for Model Predictive Control at Megahertz Rates CoRR Juan Luis Jerez, Paul J. Goulart, Stefan Richter, George A. Constantinides, Eric C. Kerrigan, Manfred Morari
2013	—	`conf`	Embedded Predictive Control on an FPGA using the Fast Gradient Method. ECC Juan Luis Jerez, Paul J. Goulart, Stefan Richter, George A. Constantinides, Eric C. Kerrigan, Manfred Morari
2013	—	`conf`	Energy-aware MPC co-design for DC-DC converters. ECC Andrea Suardi, Stefano Longo, Eric C. Kerrigan, George A. Constantinides
2013	—	`conf`	Exploiting stochastic delay variability on FPGAs with adaptive partial rerouting. FPT Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung
2013	B	`conf`	FPGA-based K-means clustering using tree-based data structures. FPL Felix Winterstein, Samuel Bayliss, George A. Constantinides
2013	—	`conf`	High-level synthesis of dynamic data structures: A case study using Vivado HLS. FPT Felix Winterstein, Samuel Bayliss, George A. Constantinides
2013	C	`conf`	Overclocking datapath for latency-error tradeoff. ISCAS Kan Shi, David Boland, George A. Constantinides
2013	—	`conf`	Revisiting the reduction circuit: A case study for simultaneous architecture and precision optimisation. FPT David Boland, George A. Constantinides
2013	B	`conf`	SMI: Slack Measurement Insertion for online timing monitoring in FPGAs. FPL Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung
2013	—	`conf`	SOAP: Structural optimization of arithmetic expressions for high-level synthesis. FPT Xitong Gao, Samuel Bayliss, George A. Constantinides
2013	A	`conf`	Word-length optimization beyond straight line code. FPGA David Boland, George A. Constantinides
2012	—	`conf`	A High Throughput FPGA-Based Implementation of the Lanczos Method for the Symmetric Extremal Eigenvalue Problem. ARC Abid Rafique, Nachiket Kapre, George A. Constantinides
2012	J	`jnl`	A Stable and Efficient Method for Solving a Convex Quadratic Program with Application to Optimal Control. SIAM J. Optim. Amir Shahzad, Eric C. Kerrigan, George A. Constantinides
2012	A	`conf`	A scalable approach for automated precision analysis. FPGA David Boland, George A. Constantinides
2012	J	`jnl`	A sparse and condensed QP formulation for predictive control of LTI systems. Autom. Juan Luis Jerez, Eric C. Kerrigan, George A. Constantinides
2012	B	`conf`	A two-stage variation-aware placement method for FPGAS exploiting variation maps classification. FPL Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung
2012	J	`jnl`	Analytical synthesis of bandwidth-efficient SDRAM address generators. Microprocess. Microsystems Samuel Bayliss, George A. Constantinides
2012	J	`jnl`	Automated Mapping of the MapReduce Pattern onto Parallel Computing Platforms. J. Signal Process. Syst. Qiang Liu, Tim Todman, Wayne Luk, George A. Constantinides
2012	C	`conf`	Correctly rounded constant integer division via multiply-add. ISCAS Theo Drane, Wai-chuen Cheung, George A. Constantinides
2012	B	`conf`	Enhancing performance of Tall-Skinny QR factorization using FPGAs. FPL Abid Rafique, Nachiket Kapre, George A. Constantinides
2012	—	`conf`	FPGA Paranoia: Testing Numerical Properties of FPGA Floating Point IP-Cores. ARC Xuan You Tan, David Boland, George A. Constantinides
2012	Misc	`conf`	Fixed Point Lanczos: Sustaining TFLOP-equivalent Performance in FPGAs for Scientific Computing. FCCM Juan Luis Jerez, George A. Constantinides, Eric C. Kerrigan
2012	Misc	`conf`	Online Measurement of Timing in Circuits: For Health Monitoring and Dynamic Voltage & Frequency Scaling. FCCM Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung
2012	J	`jnl`	Optimizing Hardware Design by Composing Utility-Directed Transformations. IEEE Trans. Computers Qiang Liu, Tim Todman, Wayne Luk, George A. Constantinides
2012	A	`conf`	Optimizing SDRAM bandwidth for custom FPGA loop accelerators. FPGA Samuel Bayliss, George A. Constantinides
2012	—	`conf`	Resource-Efficient Designs Using an Aspect-Oriented Approach. CSE José Gabriel F. Coutinho, Sujit Bhattacharya, Wayne Luk, George A. Constantinides, João M. P. Cardoso, Tiago Carvalho, Pedro C. Diniz, Zlatko Petrov
2012	—	`conf`	Towards a fixed point QP solver for predictive control. CDC Juan Luis Jerez, George A. Constantinides, Eric C. Kerrigan
2011	—	`conf`	A condensed and sparse QP formulation for predictive control. CDC/ECC Juan Luis Jerez, Eric C. Kerrigan, George A. Constantinides
2011	J	`jnl`	A parallel formulation for predictive control with nonuniform hold constraints. Annu. Rev. Control. Stefano Longo, Eric C. Kerrigan, Keck Voon Ling, George A. Constantinides
2011	—	`conf`	Accurate Floating Point Arithmetic through Hardware Error-Free Transformations. ARC Manouk V. Manoukian, George A. Constantinides
2011	A	`conf`	An FPGA implementation of a sparse quadratic programming solver for constrained predictive control. FPGA Juan Luis Jerez, George A. Constantinides, Eric C. Kerrigan
2011	J	`jnl`	An efficient algorithm for the solution of a coupled Sylvester equation appearing in descriptor systems. Autom. Amir Shahzad, Bryn Ll. Jones, Eric C. Kerrigan, George A. Constantinides
2011	—	`conf`	Application Specific Memory Access, Reuse and Reordering for SDRAM. ARC Samuel Bayliss, George A. Constantinides
2011	J	`jnl`	Bounding Variable Values and Round-Off Effects Using Handelman Representations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. David Boland, George A. Constantinides
2011	J	`jnl`	Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organization. Comput. J. Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung
2011	J	`jnl`	Guest Editors' Introduction: Surveying the Landscape of FPGA Accelerator Research. IEEE Des. Test Comput. George A. Constantinides, Nicola Nicolici
2011	A	`conf`	Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only). FPGA Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung
2011	J	`jnl`	Numerical Data Representations for FPGA-Based Scientific Computing. IEEE Des. Test Comput. George A. Constantinides, Adam B. Kinsman, Nicola Nicolici
2011	A	`conf`	Optimisation of mutually exclusive arithmetic sum-of-products. DATE Theo Drane, George A. Constantinides
2011	J	`jnl`	Optimizing memory bandwidth use and performance for matrix-vector multiplication in iterative methods. ACM Trans. Reconfigurable Technol. Syst. David Boland, George A. Constantinides
2011	—	`conf`	Parallel move blocking Model Predictive Control. CDC/ECC Stefano Longo, Eric C. Kerrigan, Keck Voon Ling, George A. Constantinides
2011	—	`conf`	Solving a positive definite system of linear equations via the matrix exponential. CDC/ECC Ammar Hasan, Eric C. Kerrigan, George A. Constantinides
2011	—	`conf`	The Krawczyk Algorithm: Rigorous Bounds for Linear Equation Solution on an FPGA. ARC Christophe Le Lann, David Boland, George A. Constantinides
2010	—	`conf`	A Fused Hybrid Floating-Point and Fixed-Point Dot-Product for FPGAs. ARC Antonio Roldao Lopes, George A. Constantinides
2010	J	`jnl`	A High Throughput FPGA-Based Floating Point Conjugate Gradient Implementation for Dense Matrices. ACM Trans. Reconfigurable Technol. Syst. Antonio Roldao Lopes, George A. Constantinides
2010	Misc	`conf`	A Scripting Engine for Combining Design Transformations. FCCM Tim Todman, Qiang Liu, Wayne Luk, George A. Constantinides
2010	—	`conf`	A fast well-conditioned interior point method for predictive control. CDC Amir Shahzad, Eric C. Kerrigan, George A. Constantinides
2010	J	`jnl`	An Automated Flow for Arithmetic Component Generation in Field-Programmable Gate Arrays. ACM Trans. Reconfigurable Technol. Syst. Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
2010	—	`conf`	An ISS and l-stability approach to forward error analysis of iterative numerical algorithms. CDC Ammar Hasan, Eric C. Kerrigan, George A. Constantinides
2010	J	`jnl`	An Optimized Hardware Architecture of a Multivariate Gaussian Random Number Generator. ACM Trans. Reconfigurable Technol. Syst. Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides
2010	Misc	`conf`	Automated Precision Analysis: A Polynomial Algebraic Approach. FCCM David Boland, George A. Constantinides
2010	C	`conf`	Customizable Composition and Parameterization of Hardware Design Transformations. DSD Tim Todman, Qiang Liu, Wayne Luk, George A. Constantinides
2010	—	`conf`	Design of a Financial Application Driven Multivariate Gaussian Random Number Generator for an FPGA. ARC Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides
2010	J	`jnl`	Efficient Heterogeneous Architecture Floorplan Optimization using Analytical Methods. ACM Trans. Reconfigurable Technol. Syst. Asma Kahoul, Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
2010	J	`jnl`	FPGA Architecture Optimization Using Geometric Programming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
2010	—	`conf`	FPGA implementation of an interior point solver for linear model predictive control. FPT Juan Luis Jerez, George A. Constantinides, Eric C. Kerrigan
2010	B	`conf`	Mapping Multiple Multivariate Gaussian Random Number Generators on an FPGA. FPL Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides
2010	—	`conf`	Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods. ARC David Boland, George A. Constantinides
2010	C	`conf`	Preconditioners for inexact interior point methods for predictive control. ACC Amir Shahzad, Eric C. Kerrigan, George A. Constantinides
2009	J	`jnl`	A Floating-point Extended Kalman Filter Implementation for Autonomous Mobile Robots. J. Signal Process. Syst. Vanderlei Bonato, Eduardo Marques, George A. Constantinides
2009	B	`conf`	Area estimation and optimisation of FPGA routing fabrics. FPL Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
2009	J	`jnl`	Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung
2009	—	`conf`	Concurrently optimizing FPGA architecture parameters and transistor sizing: Implications for FPGA design. FPT Alastair M. Smith, George A. Constantinides, Steven J. E. Wilton, Peter Y. K. Cheung
2009	J	`jnl`	Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems. IET Comput. Digit. Tech. Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung
2009	—	`conf`	Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep. ARC Asma Kahoul, George A. Constantinides, Alastair M. Smith, Peter Y. K. Cheung
2009	Misc	`conf`	More Flops or More Precision? Accuracy Parameterizable Linear Equation Solvers for Model Predictive Control. FCCM Antonio Roldao Lopes, Amir Shahzad, George A. Constantinides, Eric C. Kerrigan
2009	B	`conf`	Optimising designs by combining model-based and pattern-based transformations. FPL Qiang Liu, Tim Todman, José Gabriel de Figueiredo Coutinho, Wayne Luk, George A. Constantinides
2009	J	`jnl`	Robust Real-Time Super-Resolution on FPGA and an Application to Video Enhancement. ACM Trans. Reconfigurable Technol. Syst. Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides
2009	J	`jnl`	Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs. ACM Trans. Reconfigurable Technol. Syst. Christos-Savvas Bouganis, Sung-Boem Park, George A. Constantinides, Peter Y. K. Cheung
2009	—	`conf`	Tutorial paper: Parallel architectures for model predictive control. ECC George A. Constantinides
2009	—	`conf`	Word-Length Optimization and Error Analysis of a Multivariate Gaussian Random Number Generator. ARC Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides
2009	J	`jnl`	Word-length selection for power minimization via nonlinear optimization. ACM Trans. Design Autom. Electr. Syst. Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung
2008	—	`conf`	A High Throughput FPGA-based Floating Point Conjugate Gradient Implementation. ARC Antonio Roldao Lopes, George A. Constantinides
2008	—	`conf`	A Parallel Hardware Architecture for Image Feature Detection. ARC Vanderlei Bonato, Eduardo Marques, George A. Constantinides
2008	J	`jnl`	A Parallel Hardware Architecture for Scale and Rotation Invariant Feature Detection. IEEE Trans. Circuits Syst. Video Technol. Vanderlei Bonato, Eduardo Marques, George A. Constantinides
2008	—	`conf`	A floating-point solver for band structured linear equations. FPT Antonio Roldao Lopes, George A. Constantinides, Eric C. Kerrigan
2008	B	`conf`	An FPGA-based implementation of the MINRES algorithm. FPL David Boland, George A. Constantinides
2008	—	`conf`	Co-optimisation of datapath and memory in outer loop pipelining. FPT Kieron Turkington, George A. Constantinides, Peter Y. K. Cheung, Konstantinos Masselos
2008	B	`conf`	Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework. FPL Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung
2008	—	`conf`	Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organisation. BCS Int. Acad. Conf. Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung
2008	J	`jnl`	Custom parallel caching schemes for hardware-accelerated image compression. J. Real Time Image Process. Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung
2008	—	`conf`	FPGA-based Real-time Super-Resolution on an Adaptive Image Sensor. ARC Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides
2008	C	`conf`	Glitch-aware output switching activity from word-level statistics. ISCAS Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung, Alastair M. Smith
2008	J	`jnl`	Guest Editorial: Field Programmable Technology. J. Signal Process. Syst. George A. Constantinides, Wai-Kei Mak, Theerayod Wiangtong
2008	J	`jnl`	Integrated Floorplanning, Module-Selection, and Architecture Generationfor Reconfigurable Devices. IEEE Trans. Very Large Scale Integr. Syst. Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
2008	—	`conf`	Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGA. ARC Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides
2007	Misc	`conf`	A Hybrid Memory Sub-system for Video Coding Applications. FCCM Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung
2007	B	`conf`	A floating-point Extended Kalman Filter implementation for autonomous mobile robots. FPL Vanderlei Bonato, Eduardo Marques, George A. Constantinides
2007	Misc	`conf`	Automatic On-chip Memory Minimization for Data Reuse. FCCM Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung
2007	B	`conf`	CCDF and Monte Carlo Analysis of a Digital Polar Transmitter for Ultra-Wideband System. PIMRC Kwang-Hwee Seah, Michael Yan Wah Chia, Christos Papavassiliou, George A. Constantinides
2007	—	`conf`	Fused-Arithmetic Unit Generation for Reconfigurable Devices using Common Subgraph Extraction. FPT Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
2007	B	`conf`	On the feasibility of early routing capacitance estimation for FPGAs. FPL Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung
2007	J	`jnl`	ROM to DSP block transfer for resource constrained synthesis. IET Comput. Digit. Tech. Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung
2007	J	`jnl`	Run-Time Integration of Reconfigurable Video Processing Systems. IEEE Trans. Very Large Scale Integr. Syst. N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
2007	J	`jnl`	Special issue on Field-Programmable Technology. J. Real Time Image Process. George A. Constantinides
2006	—	`ed.`	2006 IEEE International Conference on Field Programmable Technology, FPT 2006, Bangkok, Thailand, December 13-15, 2006 FPT George A. Constantinides, Wai-Kei Mak, Phaophak Sirisuk, Theerayod Wiangtong
2006	—	`conf`	A Flexible Multi-port Caching Scheme for Reconfigurable Platforms. ARC Su-Shin Ang, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2006	B	`conf`	A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design. FPL Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
2006	Misc	`conf`	A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design. FCCM Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
2006	J	`jnl`	Accuracy-Guaranteed Bit-Width Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dong-U Lee, Altaf Abdul Gaffar, Ray C. C. Cheung, Oskar Mencer, Wayne Luk, George A. Constantinides
2006	—	`conf`	An FPGA implementation of the simplex algorithm. FPT Samuel Bayliss, Christos-Savvas Bouganis, George A. Constantinides, Wayne Luk
2006	B	`conf`	Data Reuse Exploration for FPGA Based Platforms Applied to the Full Search Motion Estimation Algorithm. FPL Konstantinos Masselos, George A. Constantinides, Qiang Liu
2006	B	`conf`	Dynamic Memory Sub-System for Reconfigurable Platforms. FPL Su-Shin Ang, George A. Constantinides
2006	B	`conf`	FPGA Based Acceleration of the Linpack Benchmark: A High Level Code Transformation Approach. FPL Kieron Turkington, Konstantinos Masselos, George A. Constantinides, Philip Heng Wai Leong
2006	C	`conf`	Fast word-level power models for synthesis of FPGA-based arithmetic. ISCAS Jonathan A. Clarke, Altaf Abdul Gaffar, George A. Constantinides, Peter Y. K. Cheung
2006	B	`conf`	High-Level Power Optimization for Digital Signal Processing in Reconfigurable Logic. FPL Jonathan A. Clarke, George A. Constantinides
2006	—	`conf`	Modeling of glitch effects in FPGA based arithmetic circuits. FPT Altaf Abdul Gaffar, Jonathan A. Clarke, George A. Constantinides
2006	—	`conf`	On-Chip Communication in Run-Time Assembled Reconfigurable Systems. ICSAMOS N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
2006	J	`jnl`	Optimal combined word-length allocation and architectural synthesis of digital signal processing circuits. IEEE Trans. Circuits Syst. II Express Briefs Gabriel Caffarena, George A. Constantinides, Peter Y. K. Cheung, Carlos Carreras, Octavio Nieto-Taladriz
2006	—	`conf`	PowerBit - power aware arithmetic bit-width optimization. FPT Altaf Abdul Gaffar, Jonathan A. Clarke, George A. Constantinides
2006	B	`conf`	Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs. FPL Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko
2006	—	`conf`	The cost of data dependence in motion vector estimation for reconfigurable platforms. FPT Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung
2006	J	`jnl`	Word-length optimization for differentiable nonlinear systems. ACM Trans. Design Autom. Electr. Syst. George A. Constantinides
2006	A	`conf`	Yield enhancements of design-specific FPGAs. FPGA Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko
2005	Misc	`conf`	A Novel 2D Filter Design Methodology for Heterogeneous Devices. FCCM Christos-Savvas Bouganis, George A. Constantinides, Peter Y. K. Cheung
2005	—	`conf`	A heuristic approach for multiple restricted multiplication. ISCAS (1) Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung
2005	—	`conf`	A novel 2D filter design methodology. ISCAS (1) Christos-Savvas Bouganis, George A. Constantinides, Peter Y. K. Cheung
2005	B	`conf`	An Analytical Approach to Generation and Exploration of Reconfigurable Architectures. FPL Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
2005	A	`conf`	Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs. FPGA Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko
2005	B	`conf`	Error Modelling of Dual FiXed-point Arithmetic and its Application in Field Programmable Logic. FPL Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides
2005	A	`conf`	Exploration of heterogeneous reconfigurable architectures (abstract only). FPGA Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
2005	B	`conf`	FPGA-Accelerated Reconstruction of Gene Regulatory Networks. FPL Iosifina Pournara, Christos-Savvas Bouganis, George A. Constantinides
2005	B	`conf`	Heterogeneity Exploration for Multiple 2D Filter Designs. FPL Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides
2005	J	`jnl`	Optimum and heuristic synthesis of multiple word-length architectures. IEEE Trans. Very Large Scale Integr. Syst. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2005	B	`conf`	Parameterized Logic Power Consumption Models for FPGA based Systems. FPL Jonathan A. Clarke, Altaf Abdul Gaffar, George A. Constantinides
2005	B	`conf`	Power and Area Optimization for Multiple Restricted Multiplication. FPL Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung
2005	B	`conf`	Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow. FPL Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung
2005	B	`conf`	Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes. FPL Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko
2004	B	`conf`	A Structured Methodology for System-on-an-FPGA Design. FPL N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
2004	Misc	`conf`	A Structured System Methodology for FPGA Based System-on-A-Chip Design. FCCM N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
2004	B	`conf`	Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation. FPL Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides
2004	J	`jnl`	Guest Editors' Introduction: Field Programmable Logic and Applications. IEEE Trans. Computers Peter Y. K. Cheung, George A. Constantinides, José T. de Sousa
2004	Misc	`conf`	Migrating Functionality from ROMS to Embedded Multipliers. FCCM Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung
2004	B	`conf`	Multiple Restricted Multiplication. FPL Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung
2004	—	`book`	Synthesis and optimization of DSP algorithms. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2004	Misc	`conf`	Word-Length Optimization of Folded Polynomial Evaluation. FCCM George A. Constantinides, Abunaser Miah, Nalin Sidahao
2003	B	`conf`	A Reconfigurable Platform for Real-Time Embedded Video Image Processing. FPL N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
2003	—	`conf`	Architectures for function evaluation on FPGAs. ISCAS (2) Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung
2003	B	`ed.`	Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings FPL Peter Y. K. Cheung, George A. Constantinides, José T. de Sousa
2003	Misc	`conf`	Perturbation Analysis for Word-length Optimization. FCCM George A. Constantinides
2003	J	`jnl`	Review of Computer arithmetic algorithms by Israel Koren. A.K. Peters. SIGACT News George A. Constantinides
2003	J	`jnl`	Synthesis of saturation arithmetic architectures. ACM Trans. Design Autom. Electr. Syst. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2003	J	`jnl`	Wordlength optimization for linear digital signal processing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2002	Misc	`conf`	Optimum Wordlength Allocation. FCCM George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2002	—	`conf`	Strassen's matrix multiplication for customisable processors. FPT Henry M. D. Ip, James D. Low, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk, Shay Ping Seng, Paul Metzgen
2002	J	`jnl`	The complexity of multiple wordlength assignment. Appl. Math. Lett. George A. Constantinides, Gerhard J. Woeginger
2001	A	`conf`	Heuristic datapath allocation for multiple wordlength systems. DATE George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2001	Misc	`conf`	The Multiple Wordlength Paradigm. FCCM George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2000	C	`conf`	Active filter synthesis based on tuneable log-domain lossy integrators. ISCAS Nikos Fragoulis, Ioannis Haritantis, George A. Constantinides
2000	Misc	`conf`	Multiple Precision for Resource Minimization. FCCM George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2000	B	`conf`	Multiple-Wordlength Resource Binding. FPL George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2000	C	`conf`	Roundoff-noise shaping in filter design. ISCAS George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
1991	Misc	`conf`	Layered DCT video coding for embedded data transmission over BISDN. ICASSP D. K. Mitrakos, George A. Constantinides
1983	Misc	`conf`	Maximum likelihood estimation of composite source models for image coding. ICASSP D. K. Mitrakos, George A. Constantinides
1982	Misc	`conf`	Composite source coding techniques for image bandwidth compression. ICASSP D. K. Mitrakos, George A. Constantinides